Interconnect Capacitance Modelling in a VDSM CMOS Technology
Résumé
This paper introduces a set of analytical formulations for 3D modelling of inter- and intra-layer capacitance. Based on real silicon data, we have developed and validated efficient and accurate analytical models that are an helpful alternative to lookup tables or numerical simulations.
Origine | Fichiers produits par l'(les) auteur(s) |
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