Interconnect Capacitance Modelling in a VDSM CMOS Technology - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier
Book Sections Year : 2002

Interconnect Capacitance Modelling in a VDSM CMOS Technology

David Bernard
  • Function : Author
ATMEL [Rousset]
Christian Landrault
  • Function : Author
  • PersonId : 845061
Conception et Test de Systèmes MICroélectroniques
Pascal Nouet
Conception et Test de Systèmes MICroélectroniques
CV

Abstract

This paper introduces a set of analytical formulations for 3D modelling of inter- and intra-layer capacitance. Based on real silicon data, we have developed and validated efficient and accurate analytical models that are an helpful alternative to lookup tables or numerical simulations.

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Micro and nanotechnologies/Microelectronics
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00268482

Submitted on : Tuesday, October 4, 2022-5:12:53 PM

Last modification on : Friday, March 24, 2023-2:53:28 PM

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lirmm-00268482 , version 1 (04-10-2022)

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David Bernard, Christian Landrault, Pascal Nouet. Interconnect Capacitance Modelling in a VDSM CMOS Technology. SOC Design Methodologies, 90, Kluwer Academic Publishers, pp.133-144, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_12⟩. ⟨lirmm-00268482⟩

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