Modeling Gate Oxide Short Defects in CMOS Minimum Transistors

Abstract : In this paper a new model is proposed for Gate Oxide Short defects based on a non-split MOS transistor. Because the MOS is not split, this model allows to simulate minimum transistors in realistic digital circuits. The construction of the model is presented in details using a comprehensive and didactic approach. It is demonstrated that the electrical behavior of the proposed model matches in a satisfactory way the defective transistor behavior.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00268527
Contributor : Christine Carvalho de Matos <>
Submitted on : Saturday, January 21, 2017 - 7:07:41 PM
Last modification on : Friday, July 20, 2018 - 12:34:01 PM
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  • HAL Id : lirmm-00268527, version 1

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Michel Renovell, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand. Modeling Gate Oxide Short Defects in CMOS Minimum Transistors. ETW: European Test Workshop, 2002, Corfu, Greece. pp.15-20. ⟨lirmm-00268527⟩

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