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Conference Papers Year : 2002

Modeling Gate Oxide Short Defects in CMOS Minimum Transistors

Abstract

In this paper a new model is proposed for Gate Oxide Short defects based on a non-split MOS transistor. Because the MOS is not split, this model allows to simulate minimum transistors in realistic digital circuits. The construction of the model is presented in details using a comprehensive and didactic approach. It is demonstrated that the electrical behavior of the proposed model matches in a satisfactory way the defective transistor behavior.
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Dates and versions

lirmm-00268527 , version 1 (21-01-2017)

Identifiers

  • HAL Id : lirmm-00268527 , version 1

Cite

Michel Renovell, Jean-Marc J.-M. Galliere, Florence Azaïs, Yves Bertrand. Modeling Gate Oxide Short Defects in CMOS Minimum Transistors. ETW: European Test Workshop, 2002, Corfu, Greece. pp.15-20. ⟨lirmm-00268527⟩
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