M. Shoji, Theory of CMOS Digital Circuits and Circuit Failures, 1992.

M. Becer and I. N. Hajj, An analytical model for delay and crosstalk estimation with application to decoupling, Proc. IEEE 1st Int. Symp. Quality Electron. Design, pp.51-57, 2000.

A. Vittal, L. H. Chen, M. Marek-sadowska, K. P. Wang, and X. Yang, Modeling crosstalk in resistive VLSI interconnections, Proc. IEEE Int. Conf. VLSI Design, pp.470-475, 1999.

M. Kuhlmann, S. S. Sapatnekar, and K. K. Parhi, Efficient crosstalk estimation, Proc. IEEE Int. Conf. Computer Design: VLSI in Computer Processors, pp.266-272, 1999.
DOI : 10.1109/iccd.1999.808435

A. B. Kahng, S. Muddu, and D. Vidhani, Noise and delay uncertainty studies for coupled RC interconnects, Proc. IEEE Int. ASIC/SOC Conf, pp.3-8, 1999.
DOI : 10.1109/asic.1999.806462

URL : http://vlsicad.ucsd.edu/Publications/Conferences/100/c100.pdf

J. Cong, D. Z. Pan, and P. V. Srinivas, Improved crosstalk modeling for noise constrained interconnect optimization, Proc. ASP-DAC Conf, pp.373-378, 2001.

G. Servel and D. Deschacht, On-chip crosstalk evaluation between adjacent interconnections, Proc. 7th IEEE Int. Conf. Electron., Circuits Syst, 2000.
DOI : 10.1109/icecs.2000.913004

J. F. Legier, E. Paleczny, G. Servel, D. Deschacht, F. Huret et al., Coupled line modelization of lossy adjacent interconnects with a full wave tangential vector finite element method, Proc. IEEE Workshop Signal Propagat. Interconnects, 2001.
URL : https://hal.archives-ouvertes.fr/hal-00152494

F. Huret, D. Deschacht, G. Servel, P. Paleczny, and P. Kennis, Full wave analysis of conductor and substrate losses in high speed VLSI Interconnects, Proc. 30th EuMC Conf, 2000.
URL : https://hal.archives-ouvertes.fr/hal-00158579

J. Zheng, Y. Hahm, V. K. Tripathi, and A. Weisshaar, CAD-oriented equivalent-circuit modeling of on-chip interconnects on lossy silicon substrate, IEEE Trans. Microwave Theory Tech, vol.48, pp.1443-1451, 2000.

, Vector Fields, vol.24