M. W. Wong and K. ,

T. Design, . Testing, .. High-speed-superconductor-microelectronics, D. Huertas, A. Vazquez et al., Heuvelmans Observer-Based Test of Analog Linear Time-Invariant Circuits13 Z. Guo and J. Savir Practical Oscillation-Based Test in Analog Integrated Filters Huertas Constrained Specification-Based Test Stimulus Generation for Analog Circuits Using Nonlinear Performance Prediction Models, 25 S. Bhattacharya and A. Chatterjee Communications MIMO Transmit Optimization for Wireless Communication Systems ......................................33 R. Choi and R. Murch

A. Power, C. Design-for-microwave-communication-system, and .. ,

C. Vsia-interface, 43 S. Ouadjaout, M.-F. Albenge, and D. Houzet Bluetooth-Based Wireless Personal Area Network for Multimedia Communication ..............47 J. Y. Khan, J. Wall, and M. A. Rashid

.. Dsp-efficiency and .. , 52 F. Carlier, F. Nouvel, and J. Citerne vi Digital Signal Processing and Architectures An Applications-Based Approach to Measuring, Multi-User Detection for CDMA Communications Based on Self Organized Neural Networks Structures...............59 J. G. Chase, C. Pretty, A. Bedarida, and P. Bettler

D. Reconfigurable, M. For-efficient, A. Video, .. Decoding, C. Pretty et al., Chase Smart Antenna Software Radio Test System, 73 V. Varshavsky and V. Marakhovsky From Low to High Level Fault Simulation and Diagnosis Behavioral Fault Simulation: Implementation and Experiments Results .................................81 D. Federici, P. Bisgambiglia, and J.-F. Santucci

.. , R. Ubar, J. Raik, E. Ivask, and M. , Brik Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits, Multi-Level Fault Simulation of Digital Systems on Decision Diagrams High Level Design Research on VHDL RTL Synthesis System.....................................99 H. Zhou, Z. Lin, and W. Cao

A. Accurate, C. Forecasting-model-for-behavioral-model-verification, .. , A. Hajjar, T. Chen et al., 111 C. Dou, S.-J. Jiang, and K.-C. Leu

I. Interconnect, . Node-for-future, .. System-on-chip-designs, C. Yeh, K. Wu et al., 116 I 123 J. Vollrath Address and Data Scrambling: Causes and Impact on Memory Tests 128 A. J. van de Goor and I. Schanstra Flash Memory Built-In Self-Test Using March-Like Algorithms, Wu A Method for Storing Fail Bit Maps in Burn-In Memory Testers............................................ 142 A. Iseno and Y. Iguchi vii Power Issues in Design and Test

C. De, F. Based, V. Battery-capacity-estimation, .. , P. E. Pascoe et al., Anbuky Power Optimization of Combinational Circuits by Input Transformations 159 R. Sankaralingam and N. A. Touba Sensor and Analog Design Test Socket Chip for Measuring Dark Current in, 167 M. L. Sheu, T. P. Sun, and F.-W. Jih

A. Low-power-high-speed-class-b-buffer, .. Amplifier-for-flat-panel-display-application, W. Pijanowska, J. Torbicz, and T. Chou, Lee Design of a Low-Voltage Instrumentation Amplifier for Enzyme-Extended-Gate Field Effect Transistor Based Urea Sensor Application

A. Silicon-piezoresistive-pressure-sensor, .. , R. Singh, L. L. Ngo, H. S. Seng et al., 187 C. A. Piña The Search for Design in Electrical Engineering Education Crisman The Development and Transfer of Advanced Technology from Universities to Industry Vos Electronics Education: A Systems Based Mechatronic Approach 209 D. A. Carnegie Boundary Scan as a Test Solution in Microelectronics 214 A. Rucinski and B. Dziurla-Rucinska Making ATE Accessible for Academic Institutions 219 W. Moorhead and S. Demidenko Teaching Integrated Circuit and Semiconductor Device Design in New Zealand: The University of Canterbury Approach Lorival PARTOS-11: An Efficient Real-Time Operating System for Low-Cost Microcontrollers, 197 R. M. Hodgson Competencies of BSc and MSc Programmes in Electrical Engineering and Student Portfolios 235 Y. Li and P. Wilson Design of a Processor to Support the Teaching of Computer Systems 240 M. Pearson, D. Armstrong, and T. McGregor Applied Science (Electronics) at the University of.. 250 R. Browne, S. Demidenko, and R. O'Driscoll Special Session on Electromagnetics and Control Design of an Auxiliary Power Distribution Network for an Electric Vehicle 257 W. Chen, S. Round, and R. Duke Analysis of Position Estimation Method for Switched Reluctance Drives 262 I. H. Al-Bahadly Conceptual Design of an All Superconducting Mini Power Plant Model

.. Hauser, P. Fulmek, F. Himmelstoss, T. Wolbank, R. Wöhrnschimmel et al., 280 D. Parker Special Session on FPGA On Biologically-Inspired Design of Fault-Tolerant Digital Systems Bondali On-Line Diagnosis and Reconfiguration of 297 M. Renovell, P. Faure, P. Prinetto, and Y. Zorian A Fault-Tolerant FPGA-Based Multi-Stage Interconnection Network for Space Sechi ix Special Session on Image Processing FPGA-Based Implementation of Variable Sized Structuring Elements for 2D Binary Morphological Operations Klimovich On the Initialization and Training Methods for Kohonen Self-Organizing Feature Maps in Color Image Quantization, 309 J. Velten and A. Kummert FPGA Implementation of a Neural Network for a Real-Time Hand Tracking System 313 M. Krips, T. Lammert, and A. Kummert Neural Networks to Solve the Problems of Control and Identification 321 X. Rui, C.-H. Chang, and T. Srikanthan An Architecture for High Speed Ultrasound Image Capture and Real-Time 3D Reconstruction

.. ,

A. Semi-generic, . System, .. Of-autonomous-mobile-mechatrons, D. A. Carnegie, .. Strategy-for-collaboration-in-robot-soccer et al., Messom Special Session on Submicron Technology A Novel Analytical Model for Evaluation of Substrate Crosstalk in VLSI Circuits Comprehensive Fault Model for Deep Submicron Digital CircuitsAbreu x Test Generation and Compaction Properties of Output Sequences and Their Use in Guiding Property-Bas ed Test Generation for Synchronous Sequential Circuits. 377 I. Pomeranz and S. M. Reddy Path-Oriented Test Data Generation of Behavioral VHDL Description, and A. Campana Random Pattern Testability of the Open Defect Detection Method Using Application of Time-Variable Electric Field, Miyase, S. Kajihara, and S. M. Reddy Generating Small Test Sets for Test Compression / Decompression Scheme Using Statistical Coding 396 H. Ichihara and T. Inoue Test Techniques and Methodologies

I. Ddt, T. Methodologies-for-very-deep-sub-micron, C. Circuits, .. , A. Chehab et al., 408 G. Peretti, E. Romero, F. Salvático, and C. Marqués Test Data Compression Using Don't-Care Identification and Statistical Encoding ............. 413 S. Kajihara, K. Taniguchi, I. Pomeranz, and S. M. Reddy

C. On, .. Of-carry-free-dividers, S. M. Aziz, S. J. , and .. , Carr Poster Papers Modeling of a Repulsive Type Magnetic Bearing for Five Axis Control under Intermittent Operation Including Eddy Current Effect 425 S. C. Mukhopadhyay A Novel Compound Type Resonant Rectifier 428 C. Chakraborty and S. C. Mukhopadhyay Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits 437 M. Pieper and A. Kummert Transmission of Data/Sketch through Telephone Lines using Gapping Technique via a Low Cost Telewriting Equipment, 434 J. Hlavicka and P. Fiser Stand-Alone Digital Real-Time Image Processing Board Based on an 447 Y. Bonhomme, P. Girard, C. Landrault, and S. Pravossoudovitch

C. Multi-carrier, C. Lines?comparison, A. Performances-with-the, and .. System, 450 S. Mallier, F. Nouvel, J.-Y. Baudais, D. Gardan, and A. Zeddam

M. Predictive, F. Control, .. , S. Tenqchen, J. Chang et al., 453 L. L. Giovanini Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits 462 J. Sosnowski and K. Szafran Pipelining Extended Givens Rotation RLS Adaptive Filters 480 W. Phipps and I. Al-Bahadly A High Voltage Amplifier for Use in, 459 M. Hashizume, M. Sato, H. Yotsuyanagi, and T. Tamesada Monitoring Parallel Interfaces in System Environment 474 Y. Liu, Z. Gao, and X. He Advanced Instruction Set Architectures for Reducing Program Memory Usage in a DSP Processor 477 P. Simonen, I. Saastamoinen, M. Kuulusa, and J. Nurmi Sensorless Speed Control in Induction Motor Drives

A. Intelligent, S. For-odour-discrimination, .. Allen, D. Bailey, S. Demidenko et al., 489 R. Singh Test Chirp Signal Generation Using Spectral Warping Piuri A New Transitive Closure Algorithm with Application to Redundancy Identification, Gaur, V. D. Agrawal, and M. L. Bushnell Test Bed for Number Plate Recognition Applications, vol.492, issue.496

A. Synthesisable, V. Model-for-an-easily-testable-generalised-multiplier, .. , S. M. Aziz, C. M. Basheer et al., Kamruzzaman xii A Comparison of Genetic Programming and Genetic Algorithms for Auto-Tuning Mobile Robot Motion Control, 507 M. Walker and C. H. Messom