D. Agrawal, B. Archambeault, J. R. Rao, and P. Rohatgi, The EM Side???Channel(s)
DOI : 10.1007/3-540-36400-5_4

D. Agrawal, J. R. Rao, and P. Rohatgi, Multi-channel Attacks, Cryptographic Hardware and Embedded Systems ? CHES 2003, pp.2-16, 2003.
DOI : 10.1007/978-3-540-45238-6_2

J. Bajard, L. Didier, and P. Kornerup, Modular multiplication and base extensions in residue number systems, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001, pp.59-65, 2001.
DOI : 10.1109/ARITH.2001.930104

J. Bajard and L. Imbert, a full RNS implementation of RSA, IEEE Transactions on Computers, vol.53, issue.6, pp.769-774, 2004.
DOI : 10.1109/TC.2004.2
URL : https://hal.archives-ouvertes.fr/lirmm-00108553

E. Biham and A. Shamir, Differential fault analysis of secret key cryptosystems, Advances in Cryptology ? CRYPTO'97 number 1294 in LNCS, pp.513-525
DOI : 10.1007/BFb0052259

D. Boneh, R. A. Demillo, and R. J. Lipton, On the Importance of Checking Cryptographic Protocols for Faults, Advances in Cryptology ? Euro- crypt'97: International Conference on the Theory and Application of Cryptographic Techniques, pp.37-51, 1997.
DOI : 10.1007/3-540-69053-0_4

C. ¸. Koç, T. Acar, and B. S. Kaliski-jr, Analyzing and comparing Montgomery multiplication algorithms, IEEE Micro, vol.16, issue.3, pp.26-33, 1996.
DOI : 10.1109/40.502403

M. Ciet, M. Neve, E. Peeters, and J. Quisquater, Parallel FPGA implementation of RSA with residue number systems ? can side-channel threats be avoided?, 46th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS- 2003), 2003.

K. Gandolfi, C. Mourtel, and F. Olivier, Electromagnetic Analysis: Concrete Results
DOI : 10.1007/3-540-44709-1_21

H. L. Garner, The residue number system, IRE Transactions on Electronic Computers, issue.8, pp.140-147, 1959.

D. M. Gordon, A Survey of Fast Exponentiation Methods, Journal of Algorithms, vol.27, issue.1, pp.129-146, 1998.
DOI : 10.1006/jagm.1997.0913

L. Goubin and J. Patarin, DES and Differential Power Analysis The ???Duplication??? Method, Cryptographic Hardware and Embedded Systems ? CHES 99, number 1717 in LNCS, pp.158-172, 1999.
DOI : 10.1007/3-540-48059-5_15

G. Hachez and J. Quisquater, Montgomery multiplication with no final subtraction: Improved results, Cryptographic Hardware and Embedded Systems -CHES 2000, pp.293-301, 1965.

W. K. Jenkins, The Design of Error Checkers for Self-Checking Residue Number Arithmetic, IEEE Transactions on Computers, vol.32, issue.4, pp.388-396, 1983.
DOI : 10.1109/TC.1983.1676240

M. Joye and S. Yen, The Montgomery Powering Ladder, Cryptographic Hardware and Embedded Systems ? CHES 2002, pp.291-302, 2002.
DOI : 10.1007/3-540-36400-5_22

S. Kawamura, M. Koike, F. Sano, and A. Shimbo, Cox-Rower Architecture for Fast Parallel Montgomery Multiplication, Advances in Cryptology -EUROCRYPT 2000, number 1807 in LNCS, pp.523-538, 2000.
DOI : 10.1007/3-540-45539-6_37

D. E. Knuth, The Art of Computer Programming Seminumerical Algorithms, 1997.

P. Kocher, J. Jaffe, and B. Jun, Differential Power Analysis, Advances in Cryptology ? CRYPTO'99, pp.388-397, 1999.
DOI : 10.1007/3-540-48405-1_25

P. C. Kocher, Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems, Advances in Cryptology -CRYPTO '96, pp.104-113, 1996.
DOI : 10.1007/3-540-68697-5_9

P. Liardet, Masquage de données décomposées dans un système de résidus. Patent, 2002.

A. J. Menezes, P. C. Van-oorschot, and S. A. Vanstone, Handbook of applied cryptography, N.W. Corporate Blvd. Boca Raton, vol.19964964, pp.33431-9868, 1997.
DOI : 10.1201/9781439821916

P. L. Montgomery, Modular multiplication without trial division, Mathematics of Computation, vol.44, issue.170, pp.519-521, 1985.
DOI : 10.1090/S0025-5718-1985-0777282-X

P. L. Montgomery, Speeding the Pollard and elliptic curve methods of factorization, Mathematics of Computation, vol.48, issue.177, pp.243-264, 1987.
DOI : 10.1090/S0025-5718-1987-0866113-7

H. Nozaki, M. Motoyama, A. Shimbo, and S. Kawamura, Implementation of RSA Algorithm Based on RNS Montgomery Multiplication, Cryptographic Hardware and Embedded Systems -CHES 2001, number 2162 in LNCS, pp.364-376, 2001.
DOI : 10.1007/3-540-44709-1_30

K. C. Posch and R. Posch, Modulo reduction in residue number systems, IEEE Transactions on Parallel and Distributed Systems, vol.6, issue.5, pp.449-454, 1995.
DOI : 10.1109/71.382314

A. P. Shenoy and R. Kumaresan, Fast base extension using a redundant modulus in RNS, IEEE Transactions on Computers, vol.38, issue.2, pp.292-297, 1989.
DOI : 10.1109/12.16508

P. R. Turner, Residue polynomial systems, Theoretical Computer Science, vol.279, issue.1-2, pp.29-49, 2002.
DOI : 10.1016/S0304-3975(00)00425-4