Optimization-based transistor sizing, IEEE J. Solid State Circuits, vol.23, pp.400-409, 1988. ,
CMOS tapered buffer, IEEE J. Solid State Circuits, vol.26, pp.1265-1269, 1991. ,
Logic decomposition algorithm for the timing optimization of multilevel logic, Proc. ICCD 89, pp.329-333 ,
Algorithms for library-specific sizing of combinational logic, Proc. DAC, pp.353-356, 1990. ,
TILOS: a posynomial programming approach to transistor sizing, Proc. Design Automation Conf, pp.326-328, 1985. ,
Logical Effort: Designing Fast CMOS Circuits, 1999. ,
Signal transition time effect on CMOS delay evaluation, IEEE trans. on Circuits and Systems: Fundamental theory and applications, vol.47, pp.1362-1369, 2000. ,
Minimum propagation delays in VLSI, IEEE J. Solid State Circuits, vol.17, pp.773-775, 1982. ,
Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay, IEEE J. Solid State Circuits, vol.29, pp.646-654, 1994. ,