S. , Test Vector Inhibiting Technique for Low Energy BIST Design // IEEE VLSI Test Symposium, vol.10, pp.407-412, 1999.

S. Gerstend?rfer and H. J. Wunderlich, LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation // IEEE International Test Conference, vol.12, pp.85-94, 1999.

X. Zhang, K. Roy, S. Bhawmik, F. Powertest-;-corno, M. Rebaudengo et al., Low Power BIST via Non-Linear Hybrid Cellular Automata // IEEE VLSI Test Symposium, A Tool for Energy Conscious Weighted Random Pattern Testing // IEEE International Conference on VLSI Design, pp.23-28, 1999.

P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures // IEEE International Test Conference, 2000.

S. Wang and S. K. Gupta, ATPG for Heat Dissipation Minimization During Test Application // IEEE International Test Conference, ATPG for Heat Dissipation Minimization for Scan Testing // ACM/ IEEE Design Automation Conference, vol.16, pp.614-619, 1994.

F. Corno, P. Prinetto, and M. Rebaudengo, Sonza Reorda M. A Test Pattern Generation Methodology for Low Power Consumption // IEEE VLSI Test Symposium, pp.453-459, 1998.

V. Dabholkar, S. Chakravarty, I. Pomeranz, S. M. Reddy, P. Girard et al., Sinanoglu O., Bayraktaroglu I., Orailoglu A. Dynamic Test Data Transformations for Average and Peak Power Reductions // IEEE European Test Workshop, Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling // IEEE Asian Test Symposium, vol.17, pp.338-343, 1998.