Metric Definition for Circuit Speed Optimization

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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00269689
Contributor : Christine Carvalho de Matos <>
Submitted on : Thursday, April 3, 2008 - 8:22:16 AM
Last modification on : Wednesday, October 24, 2018 - 9:02:05 AM

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  • HAL Id : lirmm-00269689, version 1

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Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Metric Definition for Circuit Speed Optimization. IWLS: International Workshop on Logic Synthesis, May 2003, Laguna Beach, CA, United States. ⟨lirmm-00269689⟩

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