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On the Detection of SSN-Induced Logic Errors Through On-Chip Monitoring

Abstract : Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the variations of power/ground lines at the interface between noncoherent logic blocks in order to warn that a logic error is likely to occur. This information can then be used for any scheme that takes corrective actions.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00294767
Contributor : Martine Peridier <>
Submitted on : Thursday, July 10, 2008 - 2:37:40 PM
Last modification on : Thursday, February 7, 2019 - 2:43:30 PM
Long-term archiving on: : Friday, May 28, 2010 - 11:23:46 PM

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Florence Azaïs, Laurent Larguier, Yves Bertrand, Michel Renovell. On the Detection of SSN-Induced Logic Errors Through On-Chip Monitoring. IOLTS: International On-Line Testing Symposium, Jul 2008, Rhodes, Greece. pp.233-238, ⟨10.1109/IOLTS.2008.19⟩. ⟨lirmm-00294767⟩

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