Bilateral Testing of Nano-scale Fault-tolerant Circuits, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.309-317, 2006. ,
DOI : 10.1109/DFT.2006.17
Design for testability and test generation for static redundancy system level fault-tolerant circuits, Proceedings. 'Meeting the Tests of Time'., International Test Conference, pp.812-818, 1989. ,
DOI : 10.1109/TEST.1989.82370
Fault Tolerant Systems, 2007. ,
Are Defect-Tolerant Circuits with Redundancy Really Cost Effective? Complete and Realistic Cost Model Probability that there is no defect 2 defects are equivalent to 1 couple of defect 3 defects are equivalent to 3 couples of defects ? etc, Proc. of Defect and Fault Tolerance in VLSI Systems, pp.157-165, 1997. ,