K. Bernstein, High-performance CMOS variability in the 65-nm regime and beyond, IBM Journal of Research and Development, vol.50, issue.4.5, pp.433-449, 2006.
DOI : 10.1147/rd.504.0433

K. A. Bowman, Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration, IEEE Journal of Solid-State Circuits, vol.37, issue.2, pp.183-190, 2002.
DOI : 10.1109/4.982424

S. Borkar, Parameter variations and impact on circuits and microarchitecture, Proceedings of the 40th conference on Design automation , DAC '03, 2003.
DOI : 10.1145/775832.775920

S. Chirayu and . Amin, Statistical static timing analysis: how simple can we get?, Proceedings of the 42nd DAC conference, 2005.

V. Migairou, A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation, PATMOS'07, pp.138-147, 2007.
DOI : 10.1007/978-3-540-74442-9_14

URL : https://hal.archives-ouvertes.fr/lirmm-00175076

S. Quartz and . Magma, magma-da.com/QuartzSSTA.html [8] Encounter SSTA timing System GXL ? Cadence http

B. Rebaud, Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier, 2008 IEEE Computer Society Annual Symposium on VLSI, p.8, 2008.
DOI : 10.1109/ISVLSI.2008.70

URL : https://hal.archives-ouvertes.fr/lirmm-00280809

V. Stojanovic, Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems, IEEE Journal of Solid-State Circuits, vol.34, issue.4, p.4, 1999.
DOI : 10.1109/4.753687

C. Piguet, Low Power Electronics Design Computer engineering series, 2005.

E. Salman, Exploiting Setup–Hold-Time Interdependence in Static Timing Analysis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.26, issue.6, p.6, 2007.
DOI : 10.1109/TCAD.2006.885834

V. Migairou, Statistical characterization of Library Timing Performance mC²MOS2 RFNDFF tMSNDFF mC²MOS1 tMSTGFF TNDFF TGFF-PPC 425 ps 446 ps 444 ps 427 ps 403 ps 421 ps 402 ps, PATMOS'06, pp.468-476, 2006.