A New Scan-BIST Structures to Test delay Faults in Sequential Circuits - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier
Article Dans Une Revue Journal of Electronic Testing: : Theory and Applications Année : 1999

A New Scan-BIST Structures to Test delay Faults in Sequential Circuits

Résumé

Delay testing that requires the application of consecutive two-pattern tests is not an easy task in a scan-based environment. This paper proposes a novel approach to the delay fault testing problem in scan-based sequential circuits. This solution is based on the combination of a BIST structure with a scan-based design to apply delay test pairs to the circuit under test.

Mots clés

Fichier principal
Vignette du fichier
A_New_Scan-BIST_Structures-1999.pdf (184.76 Ko) Télécharger le fichier
Origine Fichiers produits par l'(les) auteur(s)

Dates et versions

lirmm-00345797 , version 1 (20-03-2022)

Identifiants

Citer

Patrick Girard, Christian Landrault, Véronique Moreda, Serge Pravossoudovitch, Arnaud Virazel. A New Scan-BIST Structures to Test delay Faults in Sequential Circuits. Journal of Electronic Testing: : Theory and Applications, 1999, 14, pp.95-102. ⟨10.1023/A:1008305507376⟩. ⟨lirmm-00345797⟩
88 Consultations
70 Téléchargements

Altmetric

Partager

More