, International Technology Roadmap for Semiconductors (ITRS)

Y. Zorian, Testing the Monster Chip, IEEE Spectrum, vol.36, pp.54-60, 1999.

G. Hetherington, T. Fryars, N. Tamarapalli, M. Kassad, A. Hassan et al., Logic BIST for Large Industrial Designs: Real Issues and Case Studies, IEEE Int. Test Conf, pp.358-367, 1999.

J. Rajski and J. Tyszer, Arithmetic Built-In Self-Test for Embedded Systems, 1998.

H. J. Wunderlich, BIST for Systems-on-a-Chip, INTEGRATION, the VLSI Journal, vol.26, pp.55-78, 1998.

R. Dandapani, J. Patel, and J. Abraham, Design of Test Pattern Generators for Built-In Test, IEEE Int. Test Conf, pp.315-319, 1984.

C. W. Starke, Built-In Test for CMOS Circuits, IEEE Int. Test Conf, pp.309-314, 1984.

G. Edirisooriya and J. P. Robinson, Design of Low Cost ROM Based Test Generators, IEEE VLSI Test Symp, pp.61-66, 1992.

C. Fagot, P. Girard, and C. Landrault, On Using Machine Learning for Logic BIST, IEEE Int. Test Conf, pp.338-346, 1997.

B. Koenemann, LFSR-Coded Test Patterns for Scan Designs, pp.237-242, 1991.

S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers, IEEE Trans. on Computers, vol.44, issue.2, pp.223-233, 1995.
URL : https://hal.archives-ouvertes.fr/hal-00007944

S. Hellebrand, H. J. Wunderlich, and A. Hertwig, MixedMode BIST Using Embedded Processors, Journal of Electronic Testing: Theory and Applications (JETTA), vol.12, pp.127-138, 1998.

K. Chakrabarty, B. T. Murray, and V. Iyengar, Built-In Test Pattern Generation for High Performance Circuits Using Twisted-Ring Counters, IEEE VLSI Test Symp, pp.22-27, 1999.

N. A. Touba and E. J. Mccluskey, Altering a PseudoRandom Bit Sequence for Scan-Based BIST, IEEE Int. Test Conf, pp.167-175, 1996.

N. A. Touba and E. J. Mccluskey, Applying Two-Pattern Tests Using Scan-Mapping, IEEE VLSI Test Symp, pp.393-397, 1996.

C. Fagot, O. Gascuel, P. Girard, and C. Landrault, A Ring Architecture Strategy for BIST Test Pattern Generation, IEEE Asian Test Symposium, pp.418-423, 1998.
URL : https://hal.archives-ouvertes.fr/lirmm-00269518

G. Kiefer,

H. Vranken, E. J. Marinissen, and H. J. Wunderlich, Application of Deterministic Logic BIST on Industrial Circuits, IEEE Int. Test Conf, pp.105-114, 2000.

J. Savir and P. H. Bardell, On Random Pattern Test Length, IEEE Trans. on Computers, issue.6, pp.467-474, 1984.

T. Williams, Test Length in a Self-Testing Environment, IEEE Design & Test of Computers, vol.2, pp.59-63, 1985.

K. D. Wagner, C. K. Chin, and E. J. Mccluskey, PseudoRandom Testing, IEEE Trans. on Computers, vol.36, pp.332-343, 1987.

H. J. Wunderlich, Self Test Using Unequiprobable Random Patterns, IEEE Int. Symp. on Fault-Tolerant Computing, pp.258-263, 1987.

S. Pilarski and A. Pierzynska, BIST and Delay Fault Detection, IEEE Int. Test Conf, pp.236-241, 1993.

W. Wang and S. K. Gupta, Weighted Random Robust Path Delay Testing of Synthesized Multilevel Circuits, IEEE VLSI Test Symp, pp.291-297, 1994.

P. Girard, C. Landrault, V. Moreda, and S. Pravossoudovitch, An Optimized BIST Test Pattern Generator for Delay Testing, IEEE VLSI Test Symposium, pp.94-99, 1997.

C. Fagot, O. Gascuel, P. Girard, and C. Landrault, On Calculating Efficient LFSR Seeds for Built-In Self Test, IEEE European Test Workshop, pp.7-14, 1999.

E. J. Mccluskey, Verification Testing: A PseudoExhaustive Test Technique, IEEE Trans. on Computers, issue.6, pp.541-546, 1984.

G. L. Craig and C. R. Kime, Pseudo-Exhaustive Adjacency Testing: A BIST Approach for Stuck-Open Faults, IEEE Int. Test Conf, pp.126-137, 1985.

A. Vuksic and K. Fuchs, A New BIST Approach for Delay Fault Testing, IEEE VLSI Test Symp, pp.284-288, 1994.

R. C. Aitken, Nanometer Technology Effects on Fault Models for IC Testing, IEEE Computer, vol.32, issue.11, pp.46-51, 1999.

P. Nigh, W. Needham, K. Butler, P. Maxwell, and R. ,

. Aitken, An Experimental Study Comparing the Relative Effectiveness of Functional, Scan, Iddq and Delay Fault Testing, IEEE VLSI Test Symp, pp.459-464, 1997.

S. C. Ma, P. Franco, and E. J. Mccluskey, An Experimental Chip to Evaluate Test Techniques Experiment Results, IEEE Int. Test Conf, pp.663-672, 1995.

C. Chen and S. K. Gupta, BIST Test Pattern Generators for Stuck-Open and Delay Testing, pp.289-296, 1994.

A. Virazel, R. David, P. Girard, C. Landrault, and S. Pravossoudovitch, Delay Fault Testing: Effectiveness of Random SIC and Random MIC Test Sequences, pp.9-14, 2000.

M. Abramovici, M. Breuer, and A. Friedman, Digital System Testing and Testable Design, 1990.

K. Mei, Bridging and Stuck-at Faults, IEEE Trans. on Computers, issue.7, pp.720-727, 1974.

D. Lavo, B. Chess, T. Larrabee, and F. Ferguson, Diagnosing Realistic Bridging Faults with Single Stuck-at Information, IEEE Trans. on CAD, vol.3, pp.255-267, 1998.

S. Ma, I. Shaik, and R. Fetherston, A Comparison of Bridging Fault Simulation Methods, IEEE Int. Test Conf, pp.587-595, 1999.

G. L. Smith, Model for Delay Faults Based upon Paths, IEEE Int. Test Conf, pp.342-349, 1985.

A. Krstic and K. T. Cheng, Delay Fault Testing for VLSI Circuits, 1998.

R. David, Random Testing of Digital Circuits: Theory and Applications, 1998.

R. David, P. Girard, C. Landrault, S. Pravossoudovitch, and A. Virazel, On Hardware Generation of Random Single Input Change Test Sequences, 2001.

P. Girard, C. Landrault, S. Pravossoudovitch, and A. Virazel, Comparison Between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults, IEEE On-Line Testing Workshop, pp.121-126, 2000.
URL : https://hal.archives-ouvertes.fr/lirmm-00345800

. Testgen, , 1999.