A New BIST Approach for Delay Fault Testing, VLSI Test Symp, pp.284-288, 1994. ,
Built-In Test for CMOS Circuits, Int. Test Conf, pp.309-314, 1984. ,
BIST Test Pattern Generators for Stuck-Open and Delay Testing, Euro. Design & Test Conf, pp.289-296, 1994. ,
Weighted Random Robust Path Delay Testing of Synthesized Multilevel Circuits, VLSI Test Symp, pp.291-297, 1994. ,
Model for Delay faults based upon paths, Int. Test Conf, pp.309-314, 1984. ,
Random Testing of Digital Circuits, Theory and Applications, 1998. ,
Combinational Profiles of Sequential Benchmark Circuits, IEEE Int. Symp. on Circuits and Systems, pp.1929-1934, 1989. ,
, , 1999.
Robust and Non-Robust Tests for Path Delay Faults in a Combinational Circuit, Int. Test Conf, pp.1027-1034, 1987. ,
Delay Fault Testing: Effectiveness of Random SIC and Random MIC Test Sequences, IEEE European Test Workshop, pp.9-14, 2000. ,
On Hardware Generation of Random Single Input Change Test Sequences, 2001. ,