Triple Rail Logic Robustness against DPA - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier
Conference Papers Year : 2008

Triple Rail Logic Robustness against DPA

Abstract

Side channel attacks are known to be efficient techniques to retrieve secret data. Within this context, the scope of this paper is to evaluate, on and for FPGA, the robustness of triple rail logic against power analyses. More precisely, this paper aims at demonstrating that the basic concepts on which leans this logic are valid and may provide interesting design guidelines to obtain DPA (Differential Power Analysis) resistant circuits.

Keywords

Fichier principal
Vignette du fichier
2008_RECONFIG.pdf (789.42 Ko) Télécharger le fichier
Origin Files produced by the author(s)

Dates and versions

lirmm-00350573 , version 1 (28-04-2023)

Identifiers

Cite

Victor Lomné, Thomas Ordas, Philippe Maurine, Lionel Torres, Michel Robert, et al.. Triple Rail Logic Robustness against DPA. ReConFig 2008 - International Conference on Reconfigurable Computing and FPGAs, Dec 2008, Cancun, Mexico. pp.415-420, ⟨10.1109/ReConFig.2008.75⟩. ⟨lirmm-00350573⟩
137 View
24 Download

Altmetric

Share

More