, International Technology Roadmap for Semiconductors (ITRS)
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Weak Write Test Mode: an SRAM Cell Stability Design for Test Technique, Proc. of IEEE International Test Conference, pp.1043-1052, 1997. ,
An SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold, Proc. of IEEE International Test Conference, pp.1106-1115, 2004. ,
Word line Pulsing technique for stability fault detection in SRAM cells, Proc. of IEEE International Test Conference, 2005. ,
Weak cell detection in Deep-submicron SRAMs: A programmable detection technique, IEEE Journal of Solid-State Circuits, vol.41, pp.2334-2343, 2006. ,
Impact of NBTI on SRAM Read Stability and Design for Reliability, Proc. of IEEE International Symposium on Quality Electronic Design, pp.210-218, 2006. ,
Data Retention Weak Write Circuit and Method of using Same, vol.5835429, 1998. ,
Integrated Weak Write Test Mode, vol.6192001, 2001. ,
Detection of SRAM Cell Stability by Lowering Array Supply Voltage, Proc. of IEEE Asian Test Symposium, pp.268-273, 2000. ,
A Realistic Fault Model and Test Algorithms for Static Random Access Memories, IEEE Transaction on Computer, vol.9, pp.567-572, 1990. ,
Testing Semiconductor Memories: Theory and Practice, 1991. ,
An Algorithm and Design to test Random Access Memories, Proc. of IEEE International Symposium on Circuits and Systems, pp.439-442, 1992. ,
Dynamic Read Destructive Faults in Embedded SRAMs: Analysis and March Test Solution, Proc. of IEEE European Test Symposium, pp.140-145, 2004. ,
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