Differential Power Analysis, Proc. 19th International Conference on Cryptology (CRYPTO), pp.388-397, 1999. ,
DOI : 10.1007/3-540-48405-1_25
Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage, Proc. 8 th Workshop on Cryptographic Hardware and Embedded Systems (CHES), pp.242-254, 2006. ,
DOI : 10.1007/11894063_20
Design and Analysis of Dual Rail Circuits for security Applications, IEEE Transactions on Computers, vol.54, issue.4, pp.449-460, 2005. ,
Security Evaluation of Asynchronous Circuits, Proc. 5 th Workshop on Cryptographic Hardware and Embedded Systems (CHES), pp.137-151, 2003. ,
DOI : 10.1007/978-3-540-45238-6_12
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement, Design, Automation and Test in Europe, pp.424-429, 2005. ,
DOI : 10.1109/DATE.2005.124
URL : https://hal.archives-ouvertes.fr/hal-00009567
A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation, Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp.246-251, 2004. ,
DOI : 10.1109/DATE.2004.1268856
Power Analysis of an FPGA, Proc. 6 th Workshop on Cryptographic Hardware and Embedded Systems (CHES), pp.30-44, 2004. ,
DOI : 10.1007/978-3-540-28632-5_3
An investigation into the security of self-timed circuits, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings., pp.206-215, 2003. ,
DOI : 10.1109/ASYNC.2003.1199180
Automatic synthesis of asynchronous circuits from high-level specifications, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.8, issue.11, pp.1185-1205, 1989. ,
DOI : 10.1109/43.41504
Improvement of dual rail logic as a countermeasure against DPA, 2007 IFIP International Conference on Very Large Scale Integration, pp.270-275, 2007. ,
DOI : 10.1109/VLSISOC.2007.4402510
URL : https://hal.archives-ouvertes.fr/lirmm-00186174
CMOS Structures Suitable for Secure Hardware, Proc. Design, Automation and Test in Europe Conference and Exposition (DATE), pp.1414-1415, 2004. ,
Secured Structures for Secured Asynchronous QDI Circuits, Proc. 19 th International Conference on Design of Circuits and Integrated Systems (DCIS), pp.20-26, 2004. ,
URL : https://hal.archives-ouvertes.fr/hal-01393250
Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology, Proc. 5 th Workshop on Cryptographic Hardware and Embedded Systems (CHES), pp.125-136, 2003. ,
DOI : 10.1007/978-3-540-45238-6_11
A Dynamic Current Mode Logic to Counteract Power Analysis Attacks, Proc. 19 th International Conference on Design of Circuits and Integrated Systems (DCIS), 2004. ,
Delay Insensitive Encoding and Power Analysis: A Balancing Act, 11th IEEE International Symposium on Asynchronous Circuits and Systems, pp.116-125, 2005. ,
DOI : 10.1109/ASYNC.2005.18
Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks, Proc. 16 th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp.634-644, 2006. ,
DOI : 10.1007/11847083_62
URL : https://hal.archives-ouvertes.fr/lirmm-00109844
Power Balanced Gates Insensitive to Routing Capacitance Mismatch, Proc. Design, Automation and Test in Europe Conference and Exposition (DATE), pp.1280-1286, 2008. ,