Evaluation of the statistical delay quality model, ASP Design Autom. Conf, pp.305-310, 2005. ,
Resistance characterization for weak open defects, IEEE Design & Test of Computers, vol.19, issue.5, pp.18-26, 2002. ,
DOI : 10.1109/MDT.2002.1033788
High Volume Processor Test Escape, an Analysis of Defect our Test are Missing, International Test Conference, pp.25-34, 1998. ,
A circuit level fault model for resistive opens and bridges, Trans. On Design Automation of Elect. System, vol.8, pp.4-546, 2003. ,
Defective Behaviours of Resistive Opens in Interconnect Lines, European Test Symposium (ETS'05), pp.28-33, 2005. ,
DOI : 10.1109/ETS.2005.13
Testing for resistive opens and stuck opens, Proceedings International Test Conference 2001 (Cat. No.01CH37260), pp.1049-1058, 2001. ,
DOI : 10.1109/TEST.2001.966731
Fault simulation of interconnect opens in digital CMOS circuits, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97, pp.548-554, 1997. ,
DOI : 10.1109/ICCAD.1997.643593
A Persistant Diagnostic Technique for unstable defects, International Test Conference, pp.242-249, 2002. ,
Simulating Open-Via Defects, 16th Asian Test Symposium (ATS 2007), pp.265-270, 2007. ,
DOI : 10.1109/ATS.2007.72
On the fault coverage of gate delay fault detecting tests, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.16, issue.1, pp.78-94, 1997. ,
DOI : 10.1109/43.559333
Multiple tests for each gate delay fault: higher coverage and lower test application cost, IEEE International Conference on Test, 2005., 2005. ,
DOI : 10.1109/TEST.2005.1584089
The concept of resistance interval: a new parametric model for realistic resistive bridging fault, Proceedings 13th IEEE VLSI Test Symposium, pp.184-189, 1995. ,
DOI : 10.1109/VTEST.1995.512635
A Simulator of Small-Delay Faults Caused by Resistive-Open Defects, 2008 13th European Test Symposium, pp.265-270, 2008. ,
DOI : 10.1109/ETS.2008.19
URL : https://hal.archives-ouvertes.fr/lirmm-00285886
Modeling and simulation for crosstalk aggravated by weak-bridge defects between on-chip interconnects Bridging defects resistance measurements in a CMOS process, Proc. Asian Test Symposium Proc. International Test Conference, pp.440-447, 1992. ,