K. Roy, S. Mukhopadhyay, and H. Mahmoodi, Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits. Proceeding of the IEEE, vol.91, 2003.

E. Granneman, X. Pages, and E. Rosseel, Pattern-Dependent Heating of 3d Structures, 2007.

S. Mukhopadhyay, K. Kim, H. Mahmoodi, and K. Roy, Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS, IEEE Journal of Solid-State Circuits, vol.42, issue.6, 2007.

Y. Kanno, Y. Kondoh, T. Irita, K. Hirose, R. Mori et al., In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and NanosecondOrder Time Resolution, IEEE Journal of Solid-State Circuits, vol.42, issue.4, 2007.

M. Nourani and A. Radhakrishnan, Testing On-Die Process Variation in Nanometer VLSI, IEEE Design & Test of Computers, 2006.

S. Bhunia, S. Mukhopadhyay, and K. Roy, Process Variations and Process-Tolerant Design, 20th International Conference on VLSI Design, 2007.

P. Busson, N. Chawla, J. Bach, S. Le-tual, H. Singh et al., For anonymous review A 1GHz Digital Channel Multiplexer for Satellite Outdoor Unit Based on a 65nm CMOS Transceiver, 2009.

A. Epinat and R. Wilson, Yield Enhancement Methodology for CMOS Standard Cells, Proceeding of the 7th International Symposium on Quality Electronic Design, 2006.