A. Deutsch, When are transmission-line effects important for on-chip interconnections?, IEEE Transactions on Microwave Theory and Techniques, vol.45, issue.10, pp.1836-1846, 1997.
DOI : 10.1109/22.641781

S. Kundu and U. , Inductance Analysis of On-Chip Interconnects, Proceedings European Design & Test Conference, pp.252-255, 1997.

A. Lopez and D. Deschacht, Quantifying the inductive impact on output switching delay versus DSM interconnects attack, th IEEE Workshop on Signal Propagation on Interconnects, pp.11-14, 2003.
URL : https://hal.archives-ouvertes.fr/lirmm-00269532

Y. I. Ismail, On-chip inductance cons and pros, IEEE transactions on very large scale integration systems, pp.685-694, 2002.
DOI : 10.1109/TVLSI.2002.808445
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.110.7115

Y. I. Ismail, E. G. Friedman, and J. L. Neves, Figures of Merit to Characterize the Importance of On-Chip Inductance, Proceedings DAC 98, pp.560-565, 1998.

M. H. Chowdhury, Y. I. Ismail, C. V. Kashyap, and B. L. Krauter, Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), pp.197-200, 2002.
DOI : 10.1109/ISCAS.2002.1010423

D. Deschacht and A. Lopez, Performances of coupled interconnect lines: the impact of inductance and routing orientation, 18 th International Conference on VLSI Design, 2005.
URL : https://hal.archives-ouvertes.fr/lirmm-00105960

J. F. Lee, D. K. Sun, and Z. J. Cendes, Full-wave analysis of dielectric waveguides using tangential vector finite elements, MTT-39, N°8, 1991.
DOI : 10.1109/22.85399

Y. Cao, Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.10, issue.6, pp.799-805, 2002.
DOI : 10.1109/TVLSI.2002.808426

M. Muroyama, T. Ishihara, and H. Yasuura, Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption, 18 th International Workshop, pp.62-71, 2008.
DOI : 10.1109/92.365453

Y. Massoud and J. White, Simulation and modeling of the effect of substrate conductivity on coupling inductance and circuit crosstalk, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.10, issue.3, pp.286-291, 2002.
DOI : 10.1109/TVLSI.2002.1043331

A. Sinha, S. Gupta, and M. Breuer, Validation and test issues related to noise induced by parasitic inductances of VLSI interconnects, IEEE Transactions on Advanced Packaging, vol.25, issue.3, pp.329-339, 2002.
DOI : 10.1109/TADVP.2002.806802