Parallel Test of Identical Cores Using Test Elevators in 3D Circuits - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier
Conference Poster Year : 2010

Parallel Test of Identical Cores Using Test Elevators in 3D Circuits

Alberto Bosio
Conception et Test de Systèmes MICroélectroniques
Giorgio Di Natale
Conception et Test de Systèmes MICroélectroniques
CV

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Micro and nanotechnologies/Microelectronics

Martine Peridier  : Connect in order to contact the contributor

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00537857

Submitted on : Friday, November 19, 2010-3:29:29 PM

Last modification on : Friday, March 24, 2023-2:52:53 PM

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lirmm-00537857 , version 1 (19-11-2010)

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  • HAL Id : lirmm-00537857 , version 1

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Alberto Bosio, Giorgio Di Natale. Parallel Test of Identical Cores Using Test Elevators in 3D Circuits. 3D-Test: Testing Three-Dimensional Stacked Integrated Circuits, Nov 2010, Austin, TX, United States. IEEE, 1st International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, 2010. ⟨lirmm-00537857⟩

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