Effective Interconnect Networks Design in CMOS 45 nm Circuits to Joint Reductions of XT and Delay for Transmission of Very High Speed Signals - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier
Conference Papers Year : 2010

Effective Interconnect Networks Design in CMOS 45 nm Circuits to Joint Reductions of XT and Delay for Transmission of Very High Speed Signals

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Micro and nanotechnologies/Microelectronics
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00546304

Submitted on : Thursday, December 16, 2010-2:44:31 PM

Last modification on : Thursday, April 4, 2024-8:56:36 PM

Long-term archiving on : Thursday, March 17, 2011-2:37:12 AM

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lirmm-00546304 , version 1 (16-12-2010)

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  • HAL Id : lirmm-00546304 , version 1

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Sébastien de Rivaz, Alexis Farcy, Denis Deschacht, Thierry Lacrevaz, Bernard Flechet. Effective Interconnect Networks Design in CMOS 45 nm Circuits to Joint Reductions of XT and Delay for Transmission of Very High Speed Signals. EDAPS'10: Electrical Design of Advanced Package and Systems Symposium, Singapore. pp.N/A. ⟨lirmm-00546304⟩

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