SoC Yield Improvement - Using TMR Architectures for Manufacturing Defect Tolerance in Logic Cores - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier
Journal Articles International Journal On Advances in Systems and Measurements Year : 2010

SoC Yield Improvement - Using TMR Architectures for Manufacturing Defect Tolerance in Logic Cores

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Micro and nanotechnologies/Microelectronics

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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00553567

Submitted on : Friday, January 7, 2011-3:49:38 PM

Last modification on : Friday, March 24, 2023-2:52:54 PM

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lirmm-00553567 , version 1 (07-01-2011)

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  • HAL Id : lirmm-00553567 , version 1

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Julien Vial, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. SoC Yield Improvement - Using TMR Architectures for Manufacturing Defect Tolerance in Logic Cores. International Journal On Advances in Systems and Measurements, 2010, 3 (1/2), pp.1-10. ⟨lirmm-00553567⟩

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