SoC Yield Improvement - Using TMR Architectures for Manufacturing Defect Tolerance in Logic Cores
Abstract
N/A
Martine Peridier : Connect in order to contact the contributor
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00553567
Submitted on : Friday, January 7, 2011-3:49:38 PM
Last modification on : Friday, March 24, 2023-2:52:54 PM