Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line Coupling

Type de document :
Communication dans un congrès
DDECS'11: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits ans Systems, Netherlands. pp.353-358, 2011
Liste complète des métadonnées

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00592182
Contributeur : Martine Peridier <>
Soumis le : mercredi 11 mai 2011 - 15:19:36
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

Identifiants

  • HAL Id : lirmm-00592182, version 1

Collections

Citation

Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line Coupling. DDECS'11: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits ans Systems, Netherlands. pp.353-358, 2011. 〈lirmm-00592182〉

Partager

Métriques

Consultations de la notice

62