Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line Coupling - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2011

Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line Coupling

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lirmm-00592182 , version 1 (11-05-2011)

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  • HAL Id : lirmm-00592182 , version 1

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Leonardo B. Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line Coupling. DDECS'11: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits ans Systems, Netherlands. pp.353-358. ⟨lirmm-00592182⟩
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