Block- Level Added Redundancy Explicit Authentication for Parallelized Encryption and Integrity Checking of Processor- Memory Transactions - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier
Journal Articles Lecture Notes in Computer Science Year : 2010

Block- Level Added Redundancy Explicit Authentication for Parallelized Encryption and Integrity Checking of Processor- Memory Transactions

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Micro and nanotechnologies/Microelectronics

Lionel Torres  : Connect in order to contact the contributor

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00594999

Submitted on : Monday, May 23, 2011-10:36:14 AM

Last modification on : Friday, March 24, 2023-2:52:54 PM

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lirmm-00594999 , version 1 (23-05-2011)

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Lionel Torres, Reouven Elbaz, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, et al.. Block- Level Added Redundancy Explicit Authentication for Parallelized Encryption and Integrity Checking of Processor- Memory Transactions. Lecture Notes in Computer Science, 2010, 6340/2010, pp.231-260. ⟨10.1007/978-3-642-17499-5_10⟩. ⟨lirmm-00594999⟩

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