M. Toner and G. Roberts, A BIST scheme for an SNR test of a sigma-delta ADC, Proceedings of IEEE International Test Conference, (ITC), pp.805-814, 1993.
DOI : 10.1109/TEST.1993.470621

M. Toner and G. Roberts, A BIST technique for a frequency response and intermodulation distortion test of a sigma-delta ADC, Proceedings of IEEE VLSI Test Symposium, pp.60-65, 1994.
DOI : 10.1109/VTEST.1994.292333

M. J. Ohletz, Hybrid Built In Self Test (HBIST) for Mixed Analog/Digital Integrated Circuits, Proc. IEEE European Test Conference, pp.307-323, 1991.

S. K. Sunter, N. Nagi, D. , and A. Bist, A simplified polynomial-fitting algorithm for, Proc. IEEE International Test Conference, pp.389-395, 1997.

F. Azais, S. Bernard, Y. Betrand, and M. , Towards an ADC BIST scheme using the histogram test technique, Proceedings IEEE European Test Workshop, pp.53-58, 2000.
DOI : 10.1109/ETW.2000.873779

F. Azais, S. Bernard, Y. Bertrand, and M. , Implementation of a linear histogram BIST for ADCs, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, pp.590-595, 2001.
DOI : 10.1109/DATE.2001.915083

K. Arabi, B. Kaminska, and J. Rzeszut, A New Built-in Self-test Approach For Digital-to-analog And Analog-to-digital Converters, IEEE/ACM International Conference on Computer-Aided Design, pp.491-494, 1994.
DOI : 10.1109/ICCAD.1994.629860

N. Nagi, A. Chatterjee, and J. Abraham, A signature analyzer for analog and mixed-signal circuits, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp.284-287, 1994.
DOI : 10.1109/ICCD.1994.331906

M. Mahoney, DSP-Based Testing of Analog and Mixed-Signal Circuits, 1987.

M. Burns and G. W. Roberts, An Introduction to mixed-signal IC test and measurement, 2001.

J. L. Huertas, Test and design-for-testability in mixed-signal integrated circuits, 2004.
DOI : 10.1007/978-0-387-23521-9

V. Kerzérho, P. Cauvet, S. Bernard, F. Azaïs, M. Comte et al., Analogue Network of Converters " : a DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC, Proc. IEEE European Test Symposium, pp.159-164, 2006.

V. Kerzérho, P. Cauvet, S. Bernard, F. Azaïs, M. Renovell et al., ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator, VLSI Design, vol.2008, 2008.
DOI : 10.1007/s10836-006-0186-z

J. M. Janik and V. Fresnaud, A spectral approach to estimate the INL of A/D converter, Computer Standards & Interfaces, vol.29, issue.1, pp.31-37, 2007.
DOI : 10.1016/j.csi.2005.12.004

URL : https://hal.archives-ouvertes.fr/hal-00092534

V. Kerzérho, P. Cauvet, S. Bernard, F. Azaïs, M. Renovell et al., A novel DFT technique for testing complete sets of ADCs and DACs in complex SiPs, IEEE Design & Test of Computers, vol.23, issue.3, pp.234-243, 2006.
DOI : 10.1109/MDT.2006.59

H. Jiang, D. Chen, and R. L. Geiger, Dither Incorporated Deterministic Dynamic Element Matching for High Resolution ADC Test Using Extremely Low Resolution DACs, proc. IEEE International Symposium on Circuits and Systems pp, pp.4285-4288, 2005.

J. Janik, Estimation of A/D Converter Nonlinearities from complex Spectrum, Proc. International Workshop on ADC Modeling and Testing, pp.8-10, 2003.

F. Adamo, F. Attivissimo, N. Giaquinto, and M. Savino, FFT test of A/D converters to determine the integral nonlinearity, IEEE Transactions on Instrumentation and Measurement, vol.51, issue.5, pp.1050-1054, 2002.
DOI : 10.1109/TIM.2002.807795