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Timing Issues for an Efficient Use of Concurrent Error Detection Codes

Abstract : This work reveals additional timing difficulties by which concurrent error detection (CED) schemes can experience to deal efficiently with transients. It shows previously-unknown error scenarios where short-duration single transient faults in logic circuits succeed in erroneously inverting stored results but CED schemes fail in detecting even single soft errors. The paper demonstrates that typical CED code-based schemes for protecting logic circuits are not as capable as they have been claimed, and so timing conditions are suggested for a more efficient use of them.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00627427
Contributor : Rodrigo Possamai Bastos <>
Submitted on : Wednesday, September 28, 2011 - 3:45:27 PM
Last modification on : Tuesday, September 1, 2020 - 11:32:04 AM
Long-term archiving on: : Thursday, December 29, 2011 - 2:27:18 AM

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Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Timing Issues for an Efficient Use of Concurrent Error Detection Codes. LATW: Latin American Test Workshop, Mar 2011, Porto de Galinhas, Brazil. pp.1-6, ⟨10.1109/LATW.2011.5985933⟩. ⟨lirmm-00627427⟩

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