Timing Issues for an Efficient Use of Concurrent Error Detection Codes

Abstract : This work reveals additional timing difficulties by which concurrent error detection (CED) schemes can experience to deal efficiently with transients. It shows previously-unknown error scenarios where short-duration single transient faults in logic circuits succeed in erroneously inverting stored results but CED schemes fail in detecting even single soft errors. The paper demonstrates that typical CED code-based schemes for protecting logic circuits are not as capable as they have been claimed, and so timing conditions are suggested for a more efficient use of them.
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LATW: Latin American Test Workshop, Mar 2011, Porto de Galinhas, Brazil. 12th IEEE Latin American Test Workshop, pp.1-6, 2011, 〈http://www.feng.pucrs.br/~sisc/LATW/2011.html/〉. 〈10.1109/LATW.2011.5985933〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00627427
Contributeur : Rodrigo Possamai Bastos <>
Soumis le : mercredi 28 septembre 2011 - 15:45:27
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19
Document(s) archivé(s) le : jeudi 29 décembre 2011 - 02:27:18

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Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Timing Issues for an Efficient Use of Concurrent Error Detection Codes. LATW: Latin American Test Workshop, Mar 2011, Porto de Galinhas, Brazil. 12th IEEE Latin American Test Workshop, pp.1-6, 2011, 〈http://www.feng.pucrs.br/~sisc/LATW/2011.html/〉. 〈10.1109/LATW.2011.5985933〉. 〈lirmm-00627427〉

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