Time redundancy based soft-error tolerance to rescue nanometer technologies, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), pp.86-94, 1999. ,
DOI : 10.1109/VTEST.1999.766651
URL : https://hal.archives-ouvertes.fr/hal-00013764
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger, Journal of Electronic Testing, vol.1, issue.2, pp.1-3, 2008. ,
DOI : 10.1007/s10836-007-5034-2
Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.572-580, 2006. ,
DOI : 10.1109/DFT.2006.50
Simple Error Detection Methods for Hardware Implementation of Advanced Encryption Standard, IEEE Transactions on Computers, vol.55, issue.6, pp.720-731, 2006. ,
Influence of error detecting or correcting codes on the sensitivity to DPA of an AES S-box, 2009 3rd International Conference on Signals, Circuits and Systems (SCS), pp.1-5, 2009. ,
DOI : 10.1109/ICSCS.2009.5412600
URL : https://hal.archives-ouvertes.fr/hal-00469823
A logic-level model for ??-particle hits in CMOS circuits, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93, pp.538-542, 1993. ,
DOI : 10.1109/ICCD.1993.393319
Simulating Single Event Transients in VDSM ICs for Ground Level Radiation, Journal of Electronic Testing, vol.20, issue.4, pp.413-421, 2004. ,
DOI : 10.1023/B:JETT.0000039608.48856.33
URL : https://hal.archives-ouvertes.fr/hal-00013725
Is It Time for Clockless Chips, IEEE Computer, vol.38, issue.3, pp.18-21, 2005. ,