A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier
Conference Papers Year : 2011

A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits

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Micro and nanotechnologies/Microelectronics

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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00679513

Submitted on : Thursday, March 15, 2012-5:28:20 PM

Last modification on : Friday, March 24, 2023-2:52:55 PM

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lirmm-00679513 , version 1 (15-03-2012)

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  • HAL Id : lirmm-00679513 , version 1

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Ahn Duc Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. GDR SOC-SIP'11 : Colloque GDR SoC-SiP, Lyon, France. ⟨lirmm-00679513⟩

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