Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line Coupling - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier
Conference Papers Year : 2011

Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line Coupling

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Micro and nanotechnologies/Microelectronics

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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00679522

Submitted on : Thursday, March 15, 2012-5:37:42 PM

Last modification on : Friday, March 24, 2023-2:52:55 PM

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lirmm-00679522 , version 1 (15-03-2012)

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  • HAL Id : lirmm-00679522 , version 1

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Leonardo B. Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line Coupling. GDR SOC-SIP'11 : Colloque GDR SoC-SiP, Lyon, France. ⟨lirmm-00679522⟩

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