J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers, The impact of technology scaling on lifetime reliability, International Conference on Dependable Systems and Networks, 2004, pp.177-186, 2004.
DOI : 10.1109/DSN.2004.1311888

O. S. Unsal, J. W. Tschanz, K. Bowman, V. De, X. Vera et al., Impact of Parameter Variations on Circuits and Microarchitecture, IEEE Micro, vol.26, issue.6, pp.30-39, 2006.
DOI : 10.1109/MM.2006.122

T. Karnik, P. Hazucha, and J. Patel, Characterization of soft errors caused by single event upsets in CMOS processes, IEEE Transactions on Dependable and Secure Computing, vol.1, issue.2, pp.128-143, 2004.
DOI : 10.1109/TDSC.2004.14

S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K. S. Kim, Robust system design with built-in soft-error resilience, Computer, vol.38, issue.2, p.43, 2005.
DOI : 10.1109/MC.2005.70

R. Wenjing, A. Orailoglu, and R. Karri, Fault tolerant arithmetic with applications in nanotechnology based systems, 2004 International Conferce on Test, pp.472-478, 2004.
DOI : 10.1109/TEST.2004.1386983

O. Ruano, J. A. Maestro, and P. Reviriego, A Methodology for Automatic Insertion of Selective TMR in Digital Circuits Affected by SEUs, IEEE Transactions on Nuclear Science, vol.56, issue.4, pp.2091-2102, 2009.
DOI : 10.1109/TNS.2009.2014563

E. H. Neto, I. Ribeiro, M. Vieira, G. Wirth, and F. L. Kastensmidt, Using Bulk Built-in Current Sensors to Detect Soft Errors, IEEE Micro, vol.26, issue.5, pp.10-18, 2006.
DOI : 10.1109/MM.2006.103

E. H. Neto, F. L. Kastensmidt, and G. Wirth, Tbulk-BICS: A Built-In Current Sensor Robust to Process and Temperature Variations for Soft Error Detection, IEEE Transactions on Nuclear Science, vol.55, issue.4, pp.2281-2288, 2008.
DOI : 10.1109/TNS.2008.920426

G. R. Srinivasan, P. C. Murley, and H. K. Tang, Accurate, predictive modeling of soft error rate due to cosmic rays and chip alpha radiation, Proceedings of 1994 IEEE International Reliability Physics Symposium RELPHY-94, pp.12-16, 1994.
DOI : 10.1109/RELPHY.1994.307864

S. P. Athan, D. L. Landis, and S. A. , A novel built-in current sensor for I/sub DDQ/ testing of deep submicron CMOS ICs, Proceedings of 14th VLSI Test Symposium, pp.118-123, 1996.
DOI : 10.1109/VTEST.1996.510845

F. Vargas and M. Nicolaidis, SEU-tolerant SRAM design based on current monitoring, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing, pp.106-115, 1994.
DOI : 10.1109/FTCS.1994.315652

URL : https://hal.archives-ouvertes.fr/hal-00013937

B. Gill, M. Nicolaidis, F. Wolff, C. Papachristou, and S. Garverick, An efficient bics design for seus detection and correction in semiconductor memories, Design, Automation and Test in Europe, 2005. Proceedings, pp.592-597, 2005.
URL : https://hal.archives-ouvertes.fr/hal-00181657

P. Ndai, A. Agarwal, C. Qikai, and K. Roy, A soft error monitor using switching current detection, 2005 International Conference on Computer Design, pp.185-190, 2005.
DOI : 10.1109/ICCD.2005.15

A. Narsale and M. C. Huang, Variation-tolerant hierarchical voltage monitoring circuit for soft error detection, 2009 10th International Symposium on Quality of Electronic Design, pp.799-805, 2009.
DOI : 10.1109/ISQED.2009.4810395

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.332.2799

S. Hu, Berkeley short channel igfet model, Dpt. of EECS, 2005.

Z. Zhichao, W. Tao, C. Li, and Y. Jinsheng, A new bulk built-in current sensing circuit for single-event transient detection, Electrical and Computer Engineering (CCECE), 2010 23rd Canadian Conference on, pp.1-4, 2010.

G. Wirth, Bulk built in current sensors for single event transient detection in deep-submicron technologies, Microelectronics Reliability, vol.48, issue.5, pp.710-715, 2008.
DOI : 10.1016/j.microrel.2008.01.002

F. Sill, J. You, and D. Timmermann, Design of mixed gates for leakage reduction, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI , GLSVLSI '07, pp.263-2682007
DOI : 10.1145/1228784.1228851

. Synopsys, Hspice® user guide: Simulation and analysis, p.1246, 2010.

A. Balijepalli, S. Sinha, and Y. Cao, Compact modeling of carbon nanotube transistor for early stage process-design exploration, Proceedings of the 2007 international symposium on Low power electronics and design, ISLPED '07, pp.2-7, 2007.
DOI : 10.1145/1283780.1283783