tLIFTING : A Multi-level Delay-annotated Fault Simulator for Digital Circuits - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Poster Year : 2012

tLIFTING : A Multi-level Delay-annotated Fault Simulator for Digital Circuits

Abstract

This paper presents tLIFTING, an open-source fault simulator able to perform both logic and fault simulations for stuck-at faults, Single/Multiple Event Transient (SET/MET), and Single Event Upset (SEU) and Multiple Bit Upset (MBU) on digital circuits described in Verilog. tLIFTING allows delay-annotated simulation and it can deals with Standard Delay Format (SDF) files. It provides several features for accurate selection of fault location, time and period, with extensive log results meaningful for research purposes.
Fichier principal
Vignette du fichier
Poster_lu_13.pdf (838.85 Ko) Télécharger le fichier
Origin Files produced by the author(s)

Dates and versions

lirmm-00799892 , version 1 (12-03-2013)

Identifiers

  • HAL Id : lirmm-00799892 , version 1

Cite

Giorgio Di Natale, Marie-Lise Flottes, Feng Lu, Bruno Rouzeyre. tLIFTING : A Multi-level Delay-annotated Fault Simulator for Digital Circuits. DCIS 2012 - 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. , 2012. ⟨lirmm-00799892⟩
178 View
415 Download

Share

Gmail Mastodon Facebook X LinkedIn More