This paper presents tLIFTING, an open-source fault simulator able to perform both logic and fault simulations for stuck-at faults, Single/Multiple Event Transient (SET/MET), and Single Event Upset (SEU) and Multiple Bit Upset (MBU) on digital circuits described in Verilog. tLIFTING allows delay-annotated simulation and it can deals with Standard Delay Format (SDF) files. It provides several features for accurate selection of fault location, time and period, with extensive log results meaningful for research purposes.