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Models for Power-Aware Testing

Patrick Girard 1 Hans-Joachim Wunderlich 2
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Power consumption of circuits and systems receives more and more attention. In test mode, power consumption is even more critical than in system model and has severe impact on reliability, yield and test costs. This chapter describes the different types and sources of test power. Power-aware techniques for test pattern generation, design for test and test data compression are presented which allow efficient power constrained testing with minimized hardware cost and test application time.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00799927
Contributor : Isabelle Gouat <>
Submitted on : Tuesday, March 12, 2013 - 7:39:34 PM
Last modification on : Wednesday, August 28, 2019 - 3:46:02 PM

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  • HAL Id : lirmm-00799927, version 1

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Patrick Girard, Hans-Joachim Wunderlich. Models for Power-Aware Testing. Wunderlich, Hans-Joachim. Models in Hardware Testing - Lecture Notes of the Forum in honor of Christian Landrault, 43, Springer Netherlands, pp.187-215, 2010, Frontiers in Electronic Testing, 978-90-481-3281-2. ⟨lirmm-00799927⟩

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