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Conference Papers Year : 2012

An IR-Drop Simulation Principle Oriented to Delay Testing

Abstract

This paper deals with delay fault simulation of logic circuits in the context of IR-drop induced delay. An original algorithm is proposed allowing to perform a per-cycle delay simulation of the logic Block Under Test (BUT) while taking into account the whole chip IR-drop impact on the simulated block. The simulation is based on a realistic resistive model of the Power Distribution Network (PDN).
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Dates and versions

lirmm-00804254 , version 1 (25-03-2013)

Identifiers

  • HAL Id : lirmm-00804254 , version 1

Cite

Marina Aparicio Rodriguez, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell, et al.. An IR-Drop Simulation Principle Oriented to Delay Testing. DCIS 2012 - 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.404-409. ⟨lirmm-00804254⟩
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