Memory design and test represent very important issues. Memories are designed to exploit the technology limits to reach the highest storage density and high-speed access. The main consequence is that memory devices are statistically more likely to be affected by manufacturing defects. The challenge of testing SRAM memories consists in providing realistic fault models and test solutions with minimal application time. Due to the complexity of the memory device, fault modeling is not trivial. Classical memory test solutions cover the so-called 'static faults' (such as stuck-at, transition, and coupling faults) but are not sufficient to cover faults that have emerged in latest VDSM technologies and which are referred to as 'dynamic faults'. This tutorial aims at introduce and guide to new test approaches developed so far for dealing with dynamic faults in the latest generation of SRAM memories.