Power Supply Noise: A Survey on Effects and Research, IEEE Design & Test of Computers, vol.27, issue.2, pp.51-67, 2010. ,
DOI : 10.1109/MDT.2010.52
A study of path delay variations in the presence of uncorrelated power and ground supply noise, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp.164-170, 2011. ,
DOI : 10.1109/DDECS.2011.5783078
URL : https://hal.archives-ouvertes.fr/lirmm-00592000
Coping with buffer delay change due to power and ground noise, Proc. 39th Design Autom. Conf, pp.860-865, 2002. ,
DOI : 10.1145/513918.514131
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.73.9523
Static timing analysis including power supply noise effect on propagation delay in VLSI circuits, Proceedings of the 38th conference on Design automation , DAC '01, pp.295-300, 2001. ,
DOI : 10.1145/378239.378489
Vectorless analysis of supply noise induced delay variation, Proc ,
Worst-case circuit delay taking into account power supply variations, Proceedings of the 41st annual conference on Design automation , DAC '04, pp.652-657, 2004. ,
DOI : 10.1145/996566.996745
Static timing analysis considering power supply variations, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005., pp.365-371, 2005. ,
DOI : 10.1109/ICCAD.2005.1560095
Timing analysis in presence of power supply noise and ground voltage variations, Proc. EEE Int. Conf. Comput.- Aided Design, pp.1-8, 2003. ,
Gate delay estimation in STA under dynamic power supply noise, Proc. 15th Asia South Pacific Design Autom. Conf, pp.775-780, 2010. ,
Path selection and pattern generation for dynamic timing analysis considering power supply noise effects, Proc. IEEE Int. Conf. Comput. Aided Design, pp.493-496, 2000. ,
Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths, 2009 27th IEEE VLSI Test Symposium, pp.221-226, 2009. ,
DOI : 10.1109/VTS.2009.45
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.529.3426
Supply Voltage Noise Aware ATPG for Transition Delay Faults, 25th IEEE VLSI Test Symmposium (VTS'07), pp.179-186, 2007. ,
DOI : 10.1109/VTS.2007.77
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.582.2752
Power-supply noise in SoCs: ATPG, estimation and control, IEEE International Conference on Test, 2005., pp.505-516, 2005. ,
DOI : 10.1109/TEST.2005.1584011
Pattern generation for delay testing and dynamic timing analysis considering power-supply noise effects, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.20, issue.3, pp.416-425, 2001. ,
DOI : 10.1109/43.913759
Design and validation of Pentium III and Pentium 4 processors power delivery, Symp, pp.220-223, 2002. ,
Power grid physics and implications for CAD, Proc. Design Autom. Conf, pp.199-204, 2006. ,
DOI : 10.1145/1146909.1146964
Interconnect and circuit modeling techniques for full-chip power supply noise analysis, IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B, vol.21, issue.3, pp.209-215, 1998. ,
DOI : 10.1109/96.704931
Fundamentals of Parallel Logic Simulation, 23rd ACM/IEEE Design Automation Conference, pp.2-12, 1986. ,
DOI : 10.1109/DAC.1986.1586061
Introduction to Circuit Analysis, mentorgraphics.com [21] ISE Simulator, 2000. ,
High quality robust tests for path delay faults, Proc. IEEE VLSI Test Symp, pp.88-93, 1997. ,