3D power distribution network co-design for nanoscale stacked silicon ICs, 2008 IEEE-EPEP Electrical Performance of Electronic Packaging, pp.11-14, 2008. ,
DOI : 10.1109/EPEP.2008.4675863
Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication, 2007 IEEE Electrical Performance of Electronic Packaging, pp.205-208, 2007. ,
DOI : 10.1109/EPEP.2007.4387161
Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.19, issue.4, pp.647-658, 2011. ,
DOI : 10.1109/TVLSI.2009.2038165
Electrical-thermal co-analysis for power delivery networks in 3D system integration, 2009 IEEE International Conference on 3D System Integration, pp.1-4, 2009. ,
DOI : 10.1109/3DIC.2009.5306525