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Conference Poster Year : 2012

A Time-Efficient Simulation Flow for DAC Characterization & Optimization

Abstract

This paper introduces a time-efficient simulation flow for the design of Digital to Analog Converters (DAC). Evaluation of non-linearities in DACs requires intensive Monte-Carlo (MC) simulations to evaluate the impact of manufacturing mismatches. It is proposed to evaluate non-linearities in the DC domain thus limiting simulation to a reasonable time and to optimize the design for non-linearities before evaluating the speed of the converter in the transient domain for a limited set of MC runs. Characterization is based on the development of Verilog-A modules that drives the digital port of the DAC while acquiring and analyzing its analog output.
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Dates and versions

lirmm-00814994 , version 1 (18-04-2013)

Identifiers

  • HAL Id : lirmm-00814994 , version 1

Cite

Patcharee Kongpark, Laurent Latorre, Frédérick Mailly, Pascal Nouet. A Time-Efficient Simulation Flow for DAC Characterization & Optimization. DCIS 2012 - 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.298-299, 2012. ⟨lirmm-00814994⟩
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