S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi et al., Parameter variations and impact on circuits and microarchitecture, Proceedings of the 40th conference on Design automation , DAC '03, pp.338-342
DOI : 10.1145/775832.775920
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.101.7332

O. Unsal, J. Tschanz, K. Bowman, V. De, X. Vera et al., Impact of Parameter Variations on Circuits and Microarchitecture, IEEE Micro, vol.26, issue.6, pp.30-39, 2006.
DOI : 10.1109/MM.2006.122

N. Saint-jean, G. Sassatelli, P. Benoit, L. Torres, and M. Robert, HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), pp.21-28, 2007.
DOI : 10.1109/ISVLSI.2007.51
URL : https://hal.archives-ouvertes.fr/lirmm-00154074

P. Guerrier and A. Greiner, A generic architecture for on-chip packet-switched interconnections, DATE '00: Proceedings of the 2000 Design, Automation and Test in Europe Conference and Exhibition, pp.250-256, 2000.

J. William, B. Dally, and . Towles, Route packets, not wires: on-chip inteconnection networks, DAC '01: Proceedings of the 38th conference on Design automation, pp.684-689, 2001.

L. Benini and G. Micheli, Networks on chips: a new SoC paradigm, Computer, vol.35, issue.1, pp.70-78, 2002.
DOI : 10.1109/2.976921

T. Bjerregaard and S. Mahadevan, A survey of research and practices of Network-on-chip, ACM Computing Surveys, vol.38, issue.1, 2006.
DOI : 10.1145/1132952.1132953

P. Pratim-pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures, IEEE Transactions on Computers, vol.54, issue.8, pp.1025-1040, 2005.
DOI : 10.1109/TC.2005.134

D. Bertozzi and L. Benini, Xpipes: a network-on-chip architecture for gigascale systems-on-chip " , Circuits and Systems Magazine, IEEE, vol.4, issue.2, pp.18-31, 2004.

E. Beigne, F. Clermidy, P. Vivet, A. Clouard, and M. Renaudin, An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework, 11th IEEE International Symposium on Asynchronous Circuits and Systems, pp.54-63, 2005.
DOI : 10.1109/ASYNC.2005.10
URL : https://hal.archives-ouvertes.fr/hal-00009566

J. Pontes, M. Moreira, R. Soares, and N. Calazans, Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques, 2008 IEEE Computer Society Annual Symposium on VLSI, pp.347-352, 2008.
DOI : 10.1109/ISVLSI.2008.90

Y. Umit, R. Ogras, P. Marculescu, D. Choudhary, and . Marculescu, Voltage-frequency island partitioning for GALS-based Networks-on-Chip, DAC '07: Proceedings of the 44th Annual Conference on Design Automation, pp.110-115, 2007.

J. Donald and M. Martonosi, Techniques for Multicore Thermal Management, ISCA '06: Proceeding of the 33rd International Symposium on Computer Architecture, pp.78-88, 2006.
DOI : 10.1145/1150019.1136493

E. Beigne, F. Clermidy, S. Miermont, and P. Vivet, Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), pp.129-138, 2008.
DOI : 10.1109/NOCS.2008.4492732

E. Beigne, F. Clermidy, S. Miermont, A. Valentian, P. Vivet et al., A fully integrated power supply unit for fine grain DVFS and leakage control validated on low-voltage SRAMs, ESSCIRC'08: Proceeding of the 34th European Solid- State Circuits Conference, 2008.

L. Barthe, L. V. Cargnini, P. Benoit, and L. Torres, Optimizing an Open-Source Processor for FPGAs: A Case Study, 2011 21st International Conference on Field Programmable Logic and Applications, pp.551-556, 2011.
DOI : 10.1109/FPL.2011.107
URL : https://hal.archives-ouvertes.fr/lirmm-00616956

L. Barthe, L. V. Cargnini, P. Benoit, and L. Torres, The SecretBlaze: A Configurable and Cost-Effective Open-Source Soft-Core Processor, 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, pp.310-313, 2011.
DOI : 10.1109/IPDPS.2011.154

F. Moraes, N. Calazans, A. Mello, L. Moller, and L. Ost, HERMES: an infrastructure for low area overhead packet-switching networks on chip, Integration, the VLSI Journal, vol.38, issue.1, pp.69-93, 2004.
DOI : 10.1016/j.vlsi.2004.03.003

O. and R. Herveille, Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores, Revision B, vol.4, 2010.

S. Rhoads, G. Kahn, and D. B. Macqueen, Plasma -most mips i(tm) [Online] Available at: http://www.opencores.org/project,plasma [22 Coroutines and networks of parallel programming, Information Processing 77: Proceedings of the IFIP Congress, pp.993-998, 1977.

R. Busseuil, L. Barthe, G. M. Almeida, L. Ost, F. Bruguier et al., Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space Exploration, 2011 International Conference on Reconfigurable Computing and FPGAs, pp.357-362, 2011.
DOI : 10.1109/ReConFig.2011.66
URL : https://hal.archives-ouvertes.fr/hal-01139181

M. Nourani and A. Radhakrishnan, Testing On-Die Process Variation in Nanometer VLSI, IEEE Design and Test of Computers, vol.23, issue.6, 2006.
DOI : 10.1109/MDT.2006.157

S. Samaan, Parameter Variation Probing Technique, US Patent, vol.6535013, 2003.

M. Persun, Method and apparatus for measuring relative, within-die leakage current and/or providing a temperature variation profile using a leakage inverter and ring oscillators, US Patent, p.7193427, 2007.

H. Lee, Semiconductor device with speed binning test circuit and test method thereof

Z. Abuhamdeh, B. Hannagan, J. Remmers, and A. L. Crouch, A Production IR-Drop Screen on a Chip, IEEE Design & Test of Computers, vol.24, issue.3, pp.24-216, 2007.
DOI : 10.1109/MDT.2007.59

A. Drake, A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, pp.398-399, 2007.
DOI : 10.1109/ISSCC.2007.373462

S. Lopez-buedo, J. Garrido, and E. Boemo, Dynamically inserting, operating, and eliminating thermal sensors of FPGA-based systems, IEEE Transactions on Components and Packaging Technologies, vol.25, issue.4, pp.561-566, 2002.
DOI : 10.1109/TCAPT.2002.808011

A. Drake, Adaptive Techniques for Dynamic Processor Optimization, Series on Integrated Circuits and Systems, 2008.

F. Bruguier, P. Benoit, and L. Torres, Investigation of Digital Sensors for Variability Characterization on FPGAs, ReCoSoC'10: 5th International Workshop on Reconfigurable Communication-Centric Systems on Chip, France, pp.95-100
URL : https://hal.archives-ouvertes.fr/lirmm-00548801

K. Ganesan, L. John, V. Salapura, and J. Sexton, A Performance Counter Based Workload Characterization on Blue Gene/P, 2008 37th International Conference on Parallel Processing, pp.330-337, 2008.
DOI : 10.1109/ICPP.2008.57

J. M. May, MPX: Software for multiplexing hardware performance counters in multithreaded programs, Proceedings 15th International Parallel and Distributed Processing Symposium. IPDPS 2001, p.8, 2001.
DOI : 10.1109/IPDPS.2001.924955

K. Jihong and K. Yongmin, Performance analysis and tuning for a single-chip multiprocessor DSP, IEEE Concurrency, vol.5, issue.1, pp.68-79, 1997.
DOI : 10.1109/4434.580452

K. Hyun-min, Performance monitor unit design for an AXI-based multi-core SoC platform, Proceedings of the 2007 ACM symposium on Applied computing, SAC '07, pp.1565-1572

E. Faure, G. M. Almeida, M. Benabdenbi, P. Benoit, F. Clermidy et al., An inmemory monitoring database for self adaptive MP2SoCs, Design and Architectures for Signal and Image Processing 2010 Conference on, pp.97-104, 2010.

K. Niyogi and . Marculescu, Speed and voltage selection for GALS systems based on voltage/frequency islands, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005., pp.292-297
DOI : 10.1109/ASPDAC.2005.1466176

Z. T. Deniz, Y. Leblebici, and E. A. Vittoz, On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation " , Solid-State Circuits, IEEE Journal, vol.42, issue.7, pp.1593-1606, 2007.

S. Madduri, A monitor interconnect and support subsystem for multicore processors, 2009 Design, Automation & Test in Europe Conference & Exhibition, pp.761-766, 2009.
DOI : 10.1109/DATE.2009.5090766

A. Mutapcic, Processor Speed Control With Thermal Constraints, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.56, issue.9, 1994.
DOI : 10.1109/TCSI.2008.2011589
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.120.6451

H. Jung and M. Pedram, Uncertainty-Aware Dynamic Power Management in Partially Observable Domains, IEEE Trans. on VLSI Systems, 2009.

Q. Wu and P. Juang, Formal online methods for voltage/frequency control in multiple clock domain microprocessors, ACM SIGARCH Computer Architecture News, vol.32, issue.5, pp.248-259, 2004.
DOI : 10.1145/1037947.1024423

Y. Zhu and F. Mueller, Feedback EDF scheduling exploiting hardware-assisted asynchronous dynamic voltage scaling, ACM SIGPLAN Notices, vol.40, issue.7, pp.203-212, 2005.
DOI : 10.1145/1070891.1065939
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.66.9005

U. Y. Ogras and R. Marculescu, Variationadaptive feedback control for networks-on-chip with multiple clock domains, Proceedings of the 45th annual Design Automation Conference (DAC'08), pp.614-619, 2008.

A. Sharifi and H. Zhao, Feedback control for providing QoS in NoC based multicores, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), pp.1384-1389, 2010.
DOI : 10.1109/DATE.2010.5457029

G. Almeida, R. Busseuil, L. Ost, F. Bruguier, G. Sassatelli et al., PI and PID Regulation Approaches for Performance-Constrained Adaptive Multiprocessor System-on-Chip, IEEE Embedded Systems Letters, vol.3, issue.3, pp.99-100, 2011.
DOI : 10.1109/LES.2011.2166373
URL : https://hal.archives-ouvertes.fr/lirmm-00725660

M. J. Osborne and A. Rubinstein, A Course in Game Theory, 1994.

D. Puschini, F. Clermidy, P. Benoit, G. Sassatelli, and L. Torres, Adaptive energy-aware latency-constrained DVFS policy for MPSoC, 2009 IEEE International SOC Conference (SOCC), pp.89-92, 2009.
DOI : 10.1109/SOCCON.2009.5398087

D. Puschini, F. Clermidy, P. Benoit, G. Sassatelli, and L. Torres, Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC " , Design, Automation & Test in Europe Conference & Exhibition, pp.1564-1567, 2009.

D. Puschini, P. Benoit, F. Clermidy, and G. Sassatelli, A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC, International Journal of Reconfigurable Computing, vol.2008, pp.403086-403087, 2008.
DOI : 10.2307/1969529
URL : https://hal.archives-ouvertes.fr/lirmm-00333231

D. Puschini, F. Clermidy, P. Benoit, G. Sassatelli, and L. Torres, Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory, 2008 IEEE Computer Society Annual Symposium on VLSI, pp.375-380, 2008.
DOI : 10.1109/ISVLSI.2008.33
URL : https://hal.archives-ouvertes.fr/lirmm-00280678

I. Mansouri, P. Benoit, D. Puschini, L. Torres, F. Clermidy et al., Dynamic Energy Optimization in Network-on-Chip-Based System-on-Chips, Journal of Low Power Electronics, vol.6, issue.4, pp.564-577, 2010.
DOI : 10.1166/jolpe.2010.1106

J. A. Olfati-saber, R. M. Fax, and . Murray, Consensus and Cooperation in Networked Multi-Agent Systems, Proceedings of the IEEE, p.215233, 2007.
DOI : 10.1109/JPROC.2006.887293

B. Johansson, Subgradient methods and consensus algorithms for solving convex optimization problems " . Decision and Control, CDC, 2008.

I. Mansouri, F. Clermidy, P. Benoit, and L. Torres, A Runtime Distributed Cooperative Approach to Optimize Power Consumption in MPSoCs, pp.25-30
URL : https://hal.archives-ouvertes.fr/lirmm-00548820