An adaptive message passing MPSoC framework, International Journal of Reconfigurable Computing, 2009. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00373949
HeMPS -A framework for NoC-based MPSoC generation, Proceedings of the International Symposium on Circuits and Systems (ISCAS), pp.1345-1348, 2009. ,
Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs, Proceedings of the International Conference on System-on-chip (SoC, pp.87-90, 2009. ,
Incremental run-time application mapping for homogeneous NoCs with multiple voltage Levels, Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS, pp.161-166, 2007. ,
User-aware dynamic task allocation in networks-on-chip, Proceedings of the Design, Automation and Test in Europe (DATE), pp.1232-1237, 2008. ,
Run-time task allocation considering user behavior in embedded multiprocessor networks-on-chip, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.29, issue.1, pp.78-91, 2010. ,
ADAM: Run-time agent-based distributed application mapping for on-chip communication, Proceedings of the Design Automation Conference(DAC, pp.760-765, 2008. ,
Run-time spatial mapping of streaming applications to a heterogeneous multi-processor system-on-chip (MPSoC), Proceedings of the Design, Automation and Test in Europe (DATE), pp.212-217, 2008. ,
Run-time resource management in fault-tolerant network on reconfigurable chips, Proceedings of the Field Programmable Logic and Applications (FPL), pp.574-577, 2009. ,
Energy-and performance-aware mapping for regular NoC architectures, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, vol.24, issue.4, pp.551-562, 2005. ,
Executable system-level specification models containing UML-based behavioral patterns, Proceedings of the Design, Automation and Test in Europe (DATE), pp.301-306, 2007. ,
Evaluating the impact of communication latency on applications running over on-chip multiprocessing platforms: A layered approach, Proceedings of the International Conference on Industrial Informatics (INDIN), pp.148-153, 2010. ,
Fast and Accurate Transaction-Level Model of a Wormhole Network-on- Chip with Priority Preemptive Virtual Channel Arbitration, Design, Automation and Test in Europe (DATE, pp.1-6, 2011. ,
Heterogeneous versus homogeneous MPSoC approaches for a mobile LTE modem, Proceedings of the Design, Automation and Test in Europe (DATE), pp.184-189, 2010. ,
A fast and accurate NoC power and area model for early-stage design space exploration, Proceedings of the Design, Automation and Test in Europe (DATE), pp.423-428, 2009. ,
UML-based multiprocessor SoC design framework, ACM Transactions on Embedded Computing Systems, vol.5, issue.2, pp.281-320, 2006. ,
Actor-oriented models for codesign: Balancing re-use and performance. Formal Methods and Models for System Design, pp.33-56, 2004. ,
Design space exploration and prototyping for on-chip multimedia applications, Proceedings of the Design Automation Conference (DAC, pp.1-6, 2006. ,
A high level power model for Network-on-Chip (NoC) router, Computers & Electrical Engineering, vol.35, issue.6, pp.837-845, 2009. ,
Congestion-and energy-aware run-time mapping for tile-based networkon-chip architecture, Proceedings of the Frontier Computing, Theory, Technologies and Applications (FCTTA), pp.300-305, 2010. ,
Validation of executable application models mapped onto network-on-chip platforms, Proceedings of the IEEE Symposium on Industrial Embedded Systems (SIES), pp.118-125, 2008. ,
Characterising embedded applications using a UML profile, Proceedings of the International Conference on Systemon-Chip (SoC), pp.172-175, 2009. ,
Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms, International Journal of Embedded and Real-Time Communication Systems, vol.1, issue.1, pp.86-101, 2010. ,
DOI : 10.4018/jertcs.2010103005
Energyaware dynamic task mapping for NoC-based MPSoCs, Proceedings of the International Symposium on Circuits and Systems (ISCAS), pp.1676-1679, 2011. ,
Multi-task dynamic mapping onto NoC-based MP- SoCs, Proceedings of the Symposium on Integrated Circuits and Systems Design (SBCCI, pp.191-196, 2011. ,
Comparison of network-on-chip mapping algorithms targeting low energy consumption, IET Computers and Digital Techniques 2, pp.471-482, 2008. ,
Out-standing research problems in NoC design: System, microarchitecture, and circuit perspectives, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.28, issue.1, pp.3-21, 2009. ,
Power dissipation of the network-on-chip in multiprocessor system-on-chip dedicated for video coding applications, Journal of Signal Processing Systems, vol.57, issue.2, pp.139-153, 2009. ,
Closing the gap between UML-based modeling, simulation and synthesis of combined HW/SW systems, Proceedings of the Design, Automation and Test in Europe, pp.1201-1206, 2010. ,
Composable, energymanaged , real-time MPSOC platform, Proceedings of the Optimization of Electrical and Electronic Equipment (OPTIM), pp.870-876, 2010. ,
A contextual re-sources use: proof of concept through the APACHES platform, Proceedings of the Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp.42-47, 2006. ,
A high abstraction, high accuracy power estimation model for networks-on-chip, Proceedings of the Symposium on Integrated Circuits and Systems Design (SBCCI), pp.193-198, 2009. ,
Exploring NoC-based MPSoC design space with power estimation models, IEEE Design and Test of Computers, vol.28, issue.2, pp.16-29, 2011. ,
Calibration of abstract performance models for system-level design space exploration, Proc. Syst. 50, pp.99-114, 2008. ,
Dynamic power-aware mapping of applications onto heterogeneous MPSoC platforms, IEEE Trans. Indust. Info, vol.6, issue.4, pp.692-707, 2010. ,
Run-time mapping of applications to a heterogeneous SoC, Proceedings of the International Symposium on System-on-Chip (SoC, pp.78-81, 2005. ,
Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms, J. Syst. Archite, vol.56, issue.7, pp.242-255, 2010. ,
Dynamic decentralized mapping of tree-structured applications on NoC architectures, Proceedings of the Networks on Chip (NoC, pp.201-209, 2011. ,
Run time mapping of adaptive applications onto homogeneous NoC-based reconfigurable architectures, Proceedings of the Field-Programmable Technology (FPT), pp.514-517, 2009. ,
Analysis of power consumption on switch fabrics in network routers, Proceedings of the Design Automation and Conference (DAC), pp.524-529, 2002. ,