Power-Aware Testing and Test Strategies for Low Power Devices - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2010

Power-Aware Testing and Test Strategies for Low Power Devices


Managing the power consumption of circuits and systems is now considered as one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low-power devices. This tutorial provides the fundamental and advanced knowledge in this area. It is organized into three main parts. The first one gives necessary background and discusses issues arising from excessive power dissipation during manufacturing test. The second part provides comprehensive knowledge of structural and algorithmic solutions that can be used to alleviate such problems. The last part surveys low-power design techniques and shows how low-power circuits and systems can be tested safely without affecting yield and reliability. Electronic Design Automation (EDA) solutions for testing low-power devices are also covered in the last part of the tutorial.
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lirmm-00820651 , version 1 (06-05-2013)


  • HAL Id : lirmm-00820651 , version 1


Patrick Girard, Nicola Nicolici, Xiaoqing Wen. Power-Aware Testing and Test Strategies for Low Power Devices. LATW: Latin American Test Workshop, Mar 2010, Punta del Este, Uruguay. ⟨lirmm-00820651⟩
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