. Low-power, Test Pattern Generation 3.1 Low-Power ATPG 3.1.1 General Low-Power Test Generation 3.1.2 Low-Shift-Power Scan Test Generation 3.1.3 Low-Capture-Power Scan Test Generation

. Low-power, 1 Test Cube Preparation 3.3.2 Low-Shift-Power X-Filling 3.3.3 Low-Capture-Power X-Filling 3.3.4 Low-Shift-and-Capture-Power X-Filling 3.3.5 Low-Power X-Filling for Compressed Scan Testing 3.4 Low-Power Test Ordering 3.4.1 Internal-Transition-Based Ordering 3

M. Test and . Design, Bridge Defects 8.1.1 Resistive Bridge Behavior at Single and Multi-Vdd Settings 8.1.2 Cost-Effective Test for Resistive Bridges

M. Test and . Design, Open Defects 8.3 DFT for Multi-Voltage Designs 8.3.1 Multi-Voltage Aware Scan 8.3.2 Power-Managed Scan Using Adaptive Voltage Scaling