C. N. Chen and S. M. Yen, Differential Fault Analysis on AES Key Schedule and Some Countermeasures, Proc. ACISP, v. 2727 of LNCS, pp.118-129, 2003.
DOI : 10.1007/3-540-45067-X_11

P. Dusart, G. Letourneux, and O. Vivolo, Differential Fault Analysis on A.E.S, Proc. ACNS, v. 2846 of LNCS, pp.293-306, 2003.
DOI : 10.1007/978-3-540-45203-4_23

C. Lisboa, M. Erigson, and L. Carro, System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies, 12th IEEE European Test Symposium (ETS'07), pp.165-170, 2007.
DOI : 10.1109/ETS.2007.39

C. Lisboa, Using built-in sensors to cope with long duration transient faults in future technologies, 2007 IEEE International Test Conference, pp.1-10, 2007.
DOI : 10.1109/TEST.2007.4437631

C. Albrecht, Towards a Flexible Fault-Tolerant System-on-Chip, Proc. ARC, pp.83-90, 2009.
DOI : 10.1007/BF03345439

S. Z. Shazli and M. B. Tahoori, Transient Error Detection and Recovery in Processor Pipelines, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.304-312, 2009.
DOI : 10.1109/DFT.2009.38

R. P. Bastos, G. D. Natale, M. Flottes, and B. Rouzeyre, A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, pp.302-308, 2011.
DOI : 10.1109/DFT.2011.15
URL : https://hal.archives-ouvertes.fr/lirmm-00701789

B. Gill, An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories, Pro. DATE, IEEE, pp.592-597, 2005.
URL : https://hal.archives-ouvertes.fr/hal-00181657

E. H. Neto, Using Bulk Built-in Current Sensors to Detect Soft Errors, IEEE Micro, vol.26, issue.5, pp.10-18, 2006.
DOI : 10.1109/MM.2006.103

S. Mitra and E. Mccluskey, Which concurrent error detection scheme to choose ?, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159), pp.985-994, 2000.
DOI : 10.1109/TEST.2000.894311

M. Nicolaidis, Time redundancy based soft-error tolerance to rescue nanometer technologies, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), pp.86-94, 1999.
DOI : 10.1109/VTEST.1999.766651
URL : https://hal.archives-ouvertes.fr/hal-00013764

L. Anghel and M. Nicolaidis, Cost Reduction and Evaluation of a Temporary Faults Detecting Technique, Proc. DATE, IEEE, pp.591-598, 2000.
URL : https://hal.archives-ouvertes.fr/hal-00013756

D. Ernst, Razor: a low-power pipeline based on circuit-level timing speculation, 22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449), pp.7-18, 2003.
DOI : 10.1109/MICRO.2003.1253179

K. Bowman, Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance, IEEE Journal of Solid-State Circuits, vol.44, issue.1, pp.49-63, 2009.
DOI : 10.1109/JSSC.2008.2007148

R. P. Bastos, How to sample results of concurrent error detection schemes in transient fault scenarios?, 2011 12th European Conference on Radiation and Its Effects on Components and Systems, pp.635-642, 2011.
DOI : 10.1109/RADECS.2011.6131361
URL : https://hal.archives-ouvertes.fr/lirmm-00701776

S. Das, RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance, IEEE Journal of Solid-State Circuits, vol.44, issue.1, pp.32-48, 2009.
DOI : 10.1109/JSSC.2008.2007145

M. M. Kermani and A. R. Masoleh, Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.572-580, 2006.
DOI : 10.1109/DFT.2006.50

C. Lisboa and L. Carro, XOR-Based Low Cost Checkers for Combinational Logic, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, pp.281-289, 2008.
DOI : 10.1109/DFT.2008.35

D. Rossi, M. Omanã, and C. Metra, Transient Fault and Soft Error On-die Monitoring Scheme, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.391-398, 2010.
DOI : 10.1109/DFT.2010.53

D. J. Palframan, N. S. Kim, and M. H. Lipasti, Time redundant parity for low-cost transient error detection, 2011 Design, Automation & Test in Europe, 2011.
DOI : 10.1109/DATE.2011.5763017

R. P. Bastos, Timing issues for an efficient use of concurrent error detection codes, 2011 12th Latin American Test Workshop (LATW), pp.1-6, 2011.
DOI : 10.1109/LATW.2011.5985933
URL : https://hal.archives-ouvertes.fr/lirmm-00627427