B. Yang, K. Wu, and R. Karri, Secure scan, Proceedings of the 42nd annual conference on Design automation , DAC '05, pp.2287-2293, 2006.
DOI : 10.1145/1065579.1065617

B. Yang, K. Wu, and R. Karri, Scan based side channel attack on dedicated hardware implementations of data encryption standard, Proc. IEEE Int. Test Conf, pp.339-344, 2004.

Y. Wu and P. Macdonald, Testing ASICs with multiple identical cores, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst, vol.22, issue.3, pp.327-336, 2003.

K. J. Balakrishnan, G. Giles, and J. Wingfield, Test Access Mechanism in the Quad-Core AMD Opteron Microprocessor, IEEE Design & Test of Computers, vol.26, issue.1, pp.52-59, 2009.
DOI : 10.1109/MDT.2009.17

D. Andreu, System and method for wirelessly testing integrated circuits, 2011.
URL : https://hal.archives-ouvertes.fr/lirmm-00767777

F. Poehl, M. Beck, R. Arnold, J. Rzeha, T. Rabenalt et al., On-chip evaluation, compensation and storage of scan diagnosis data, IET Computers & Digital Techniques, vol.1, issue.3, pp.207-212, 2007.
DOI : 10.1049/iet-cdt:20060129

G. Chiu and J. C. Li, A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.20, issue.1, pp.126-134, 2012.
DOI : 10.1109/TVLSI.2010.2089071

K. Rosenfeld and R. Karri, Attacks and Defenses for JTAG, IEEE Design & Test of Computers, vol.27, issue.1, pp.36-47, 2010.
DOI : 10.1109/MDT.2010.9

C. J. Clark, Anti-tamper JTAG TAP design enables DRM to JTAG registers and P1687 on-chip instruments, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp.19-24, 2010.
DOI : 10.1109/HST.2010.5513119

D. Hely, F. Bancel, N. Berard, M. L. Flottes, and B. Rouzeyre, Test Control for Secure Scan Designs, European Test Symposium (ETS'05), pp.190-195, 2005.
DOI : 10.1109/ETS.2005.36

URL : https://hal.archives-ouvertes.fr/lirmm-00106011

D. Hely, M. Flottes, F. Bancel, B. Rouzeyre, N. Berard et al., Scan design and secure chip [secure IC testing], Proceedings. 10th IEEE International On-Line Testing Symposium, pp.219-224, 2004.
DOI : 10.1109/OLT.2004.1319691

G. Sengar, D. Mukhopadhyay, and D. R. Chowdhury, Secured Flipped Scan-Chain Model for Crypto-Architecture, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.26, issue.11, pp.2080-2084, 2007.
DOI : 10.1109/TCAD.2007.906483

H. Fujiwara and M. E. Obien, Secure and testable scan design using extended de Bruijn graphs, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), pp.413-418, 2010.
DOI : 10.1109/ASPDAC.2010.5419845

J. Da-rolt, G. Di-natale, M. Flottes, and B. Rouzeyre, New security threats against chips containing scan chain structures, 2011 IEEE International Symposium on Hardware-Oriented Security and Trust, pp.110-115, 2011.
DOI : 10.1109/HST.2011.5955005

URL : https://hal.archives-ouvertes.fr/lirmm-00599690

L. Chunsheng and Y. Huang, Effects of embedded decompression and compaction architectures on side-channel attack resistance, Proc. IEEE VLSI Test Symp, pp.461-468, 2007.

P. Kocher, J. Jaffe, and B. Jun, Differential Power Analysis, Proc. Int. Cryptol. Conf. Adv. Cryptol, pp.388-397, 1999.
DOI : 10.1007/3-540-48405-1_25

P. Dusart, G. Letourneux, and O. Vivolo, Differential Fault Analysis on A.E.S, Applied Cryptography and Network Security, pp.293-306, 2003.
DOI : 10.1007/978-3-540-45203-4_23

A. Moradi, T. Eisenbarth, A. Poschmann, C. Rolfes, C. Paar et al., Information leakage of flip-flops in DPA-resistant logic styles, Proc. IACR Cryptology ePrint Archive, pp.188-188, 2008.