Cellule mémoire volatile/non-volatile

Abstract : The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first resistance switching element (202) programmed to have a first resistance; and a second transistor (104) coupled between a second storage node (108) and a second resistance switching element (204) programmed to have a second resistance, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; and control circuitry (602) adapted to store a data value (DNV) at said first and second storage nodes by coupling said first and second storage nodes to a first supply voltage (VDD, GND), the data value being determined by the relative resistances of the first and second resistance switching elements.
Type de document :
Brevet
France, N° de brevet: FR 2970589 (B1) WO/2012/098181 (A1). 2013, pp.N/A
Liste complète des métadonnées

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00861516
Contributeur : Isabelle Gouat <>
Soumis le : jeudi 12 septembre 2013 - 19:27:02
Dernière modification le : vendredi 9 mars 2018 - 16:38:03

Identifiants

  • HAL Id : lirmm-00861516, version 1

Citation

Gregory Pendina, Yoann Guillemenet, Guillaune Prenat, Kholdoun Tork, Lionel Torres. Cellule mémoire volatile/non-volatile. France, N° de brevet: FR 2970589 (B1) WO/2012/098181 (A1). 2013, pp.N/A. 〈lirmm-00861516〉

Partager

Métriques

Consultations de la notice

132