F. H. Irons, D. M. Hummels, and S. P. Kennedy, Improved compensation for analog-to-digital converters, IEEE Transactions on Circuits and Systems, vol.38, issue.8, pp.958-961, 1991.
DOI : 10.1109/31.85640

S. Medawar, P. Händel, N. Björsell, and M. Jansson, ADC Characterization By Dynamic Integral Nonlinearity, IMEKO 13th Workshop on ADC Modelling and Testing, pp.1037-1042, 2008.

H. Fraz, N. Bjorsell, J. S. Kenney, and R. Sperlich, Prediction of Harmonic Distortion in ADCs using dynamic Integral Non-Linearity model, 2009 IEEE Behavioral Modeling and Simulation Workshop, pp.102-107, 2009.
DOI : 10.1109/BMAS.2009.5338881

B. Provost and E. Sanchez-sinencio, On-chip ramp generators for mixed-signal BIST and ADC self-test, IEEE Journal of Solid-State Circuits, vol.38, issue.2, pp.263-273, 2003.
DOI : 10.1109/JSSC.2002.807415

J. Wang, E. Sanchez-sinencio, and F. Maloberti, Very linear ramp-generators for high resolution ADC BIST and calibration, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144), pp.908-911, 2000.
DOI : 10.1109/MWSCAS.2000.952901

B. K. Vasan, S. K. Sudani, D. J. Chen, and R. L. Geiger, Sinusoidal signal generation for production testing and BIST applications, 2012 IEEE International Symposium on Circuits and Systems, pp.2601-2604, 2012.
DOI : 10.1109/ISCAS.2012.6271837

F. Azaïs, S. Bernard, Y. Bertrand, X. Michel, and M. , A low-cost adaptive ramp generator for analog BIST applications, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, pp.266-271, 2001.
DOI : 10.1109/VTS.2001.923449

S. Bernard, F. Azaïs, M. Comte, O. Potin, V. Kerzérho et al., Adaptive LUT-based system for in situ ADC auto-correction, 2010 IEEE 16th International Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW), pp.1-6
DOI : 10.1109/IMS3TW.2010.5502995

URL : https://hal.archives-ouvertes.fr/lirmm-00494424

M. Mahoney, DSP-Based Testing of Analog and Mixed- Signal Circuits, 1987.

S. Max, IEEE Std 1241: the benefits and risks of ADC histogram testing, IMTC 2001. Proceedings of the 18th IEEE Instrumentation and Measurement Technology Conference. Rediscovering Measurement in the Age of Informatics (Cat. No.01CH 37188), pp.704-709, 2001.
DOI : 10.1109/IMTC.2001.928910

F. Azaïs, S. Bernard, Y. Bertrand, and M. , Implementation of a linear histogram BIST for ADCs, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, pp.590-595, 2001.
DOI : 10.1109/DATE.2001.915083

J. Ren, J. Feng, and H. Ye, A Novel Linear Histogram BIST for ADC, 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), pp.2099-2102, 2008.

M. Da-glória-cataldi-flores, M. Negreiros, L. Carro, and A. A. Susin, INL and DNL estimation based on noise ADC test, Proceedings of the 20th IEEE Instrumentation Technology Conference (Cat. No.03CH37412), pp.1391-1395, 2004.
DOI : 10.1109/IMTC.2003.1207971

A. J. Ginés, E. J. Peralías, and A. Rueda, An adaptive BIST for INL estimation of ADCs without histogram evaluation, 2010 IEEE 16th International Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW), pp.1-6, 2010.
DOI : 10.1109/IMS3TW.2010.5502997

B. K. Vasan, D. J. Chen, and R. L. Geiger, ADC Integral Non- Llinearity Testing with Low Linearity Monotonic Signals, IEEE Instrumentation and Measurement Technology Conference (I2MTC), pp.1-5, 2011.

E. Korhonen, C. Wegener, and . Kostamovaara, Combining the Standard Histogram Method and a Stimulus Identification Algorithm for A/D Converter INL Testing With a Low-Quality Sine Wave Stimulus, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.57, issue.6, pp.1166-1174, 2010.
DOI : 10.1109/TCSI.2009.2030096

M. A. Jalon and E. Peralias, ADC non-linearity low-cost test through a simplified Double-Histogram method, 2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop, pp.47-58, 2010.
DOI : 10.1109/IMS3TW.2009.5158686

M. J. Barragan, D. Vazquez, and A. Rueda, Analog Sinewave Signal Generators for Mixed-Signal Built-in Test Applications, Journal of Electronic Testing, vol.36, issue.12, pp.305-320, 2011.
DOI : 10.1007/s10836-010-5192-5

V. Kerzérho, V. Fresnaud, D. Dallet, S. Bernard, and L. Bossuet, Fast Digital Post-Processing Technique for INL Correction of ADC: Validation on a 12-bit F&I ADC, IEEE Transactions on Instrumentation & Measurement, 2010.