A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults

This work proposes a novel built-in current sensor for detecting transient faults of short and long duration as well as multiple faults in combinational and sequential logic. Unlike prior similar strategies, which are formed by pairs of PMOS and NMOS sensors, the proposed scheme is a single sensor connected to PMOS and NMOS bulks of the monitored logic. In comparison with existing transient-fault mitigation techniques, the paper presents very competitive results that indicate no performance penalty, and overheads of only 26 % in power consumption and 23 % in area.

Mots clés

Transient faults Built-in current sensors Concurrent detection Fault attacks Fault tolerance Security Soft errors

Domaines

Micro et nanotechnologies/Microélectronique

Fichier principal

abstract_2_Possamai_Bastos_2013-04-08_23_41_52_paper-radecs-20130408-rpb.pdf (1.01 Mo)

Origine	Fichiers produits par l'(les) auteur(s)

Marie-Lise Flottes : Connectez-vous pour contacter le contributeur

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00968621

Soumis le : mercredi 5 octobre 2016-15:50:24

Dernière modification le : mercredi 18 décembre 2024-10:09:17

Archivage à long terme le : vendredi 6 janvier 2017-13:55:07

Dates et versions

lirmm-00968621 , version 1 (05-10-2016)

Identifiants

HAL Id : lirmm-00968621 , version 1
DOI : 10.1109/PATMOS.2013.6662169

Citer

Rodrigo Possamai Bastos, Frank Sill Torres, Jean-Max Dutertre, Marie-Lise Flottes, Giorgio Di Natale, et al.. A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2013, Karlsruhe, Germany. pp.157-163, ⟨10.1109/PATMOS.2013.6662169⟩. ⟨lirmm-00968621⟩

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