A frequency leakage model for SCA

Abstract : This paper introduces a leakage model in the frequency domain to enhance the efficiency of Side Channel Attacks of CMOS circuits. While usual techniques are focused on noise removal around clock harmonics, we show that the actual leakage is not necessary located in those expected bandwidths as experimentally observed by E. Mateos and C.H. Gebotys in 2010. We start by building a theoretical modeling of power consumption and electromagnetic emanations before deriving from it a criterion to guide standard attacks. This criterion is then validated on real experiments, both on FPGA and ASIC, showing an impressive increase of the yield of SCA.
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Communication dans un congrès
HOST'2014: International Symposium on Hardware-Oriented Security and Trust, May 2014, Arlington, VA, United States. IEEE, Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp.97-100, Hardware-Oriented Security and Trust. 〈10.1109/HST.2014.6855577〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01096058
Contributeur : Philippe Maurine <>
Soumis le : mardi 16 décembre 2014 - 16:47:05
Dernière modification le : mercredi 24 octobre 2018 - 09:02:05

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Sébastien Tiran, Sébastien Ordas, Yannick Teglia, Michel Agoyan, Philippe Maurine. A frequency leakage model for SCA. HOST'2014: International Symposium on Hardware-Oriented Security and Trust, May 2014, Arlington, VA, United States. IEEE, Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp.97-100, Hardware-Oriented Security and Trust. 〈10.1109/HST.2014.6855577〉. 〈lirmm-01096058〉

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