Laser shots on secure ICs have proven to be a very effective mean to perform fault attacks. As depicted in Figure 1, due to photo-electric effects, laser can induce transient pulses on gate output and thus generate faults in downstream registers. It is therefore essential for designers of secure devices to have a CAD environment to check the resistance of the circuits against laser attacks and/or to validate the effectiveness of countermeasures during early stage of the design cycle without requiring actually manufacturing some prototype. In this paper we present a complete environment for modeling and simulating the laser effects on circuits during the synthesis step. It takes into account laser parameters and relies on circuit layout information.