Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems, Advances in Cryptology, pp.104-113, 1996. ,
DOI : 10.1007/3-540-68697-5_9
Design and Validation Strategies for Obtaining Assurance in Countermeasures to Power Analysis and Related Attacks, Proceedings of the NIST Physical Security Workshop, 2005. ,
Differential Power Analysis in the Presence of Hardware Countermeasures, Cryptographic Hardware and Embedded SystemsCHES, pp.252-263, 2000. ,
DOI : 10.1007/3-540-44499-8_20
Differential Power Analysis, Advances in Cryptology, pp.388-397, 1999. ,
DOI : 10.1007/3-540-48405-1_25
Correlation Power Analysis with a Leakage Model, Proceedings of the 2004 Cryptographic Hardware and Embedded Systems Workshop, pp.16-29, 2004. ,
DOI : 10.1007/978-3-540-28632-5_2
The SecretBlaze: A Configurable and Cost-Effective Open-Source Soft-Core Processor, 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, pp.305-308, 2011. ,
DOI : 10.1109/IPDPS.2011.154
DES and Differential Power Analysis The ???Duplication??? Method, Proceedings of the 1999 Cryptographic Hardware and Embedded Systems Workshop, pp.158-172, 1999. ,
DOI : 10.1007/3-540-48059-5_15
Private Circuits: Securing Hardware against Probing Attacks, Advances in Cryptology, pp.463-481, 2003. ,
DOI : 10.1007/978-3-540-45146-4_27
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.115.9436
A Side-Channel Analysis Resistant Description of the AES S-Box, Fast Software Encryption, pp.413-423, 2005. ,
DOI : 10.1007/11502760_28
Higher Order Masking of the AES, Topics in Cryptology, The Cryptographers Track at the RSA Conference, pp.208-225, 2006. ,
DOI : 10.1007/11605805_14
Provable Secure Higher-Order Masking of AES, Proceedings of the 2010 Cryptographic Hardware and Embedded Systems Workshop, 2010. ,
Towards Sound Approaches to Counteract Power-Analysis Attacks, Advances in Cryptology, pp.398-412, 1999. ,
DOI : 10.1007/3-540-48405-1_26
Securing the AES Finalists Against Power Analysis Attacks, Proceedings of the 7th International Workshop on Fast Software Encryption, pp.150-164, 2000. ,
DOI : 10.1007/3-540-44706-7_11
A Secure D Flip-Flop against Side Channel Attacks, Proceedings of the 21st International Conference on Integrated Circuit and System Design: Power And Timing Modeling, Optimization, and Simulation, pp.331-340, 2011. ,
DOI : 10.1007/978-3-642-24154-3_33
URL : https://hal.archives-ouvertes.fr/lirmm-00762027
Evaluation of countermeasure implementations based on Boolean masking to thwart side-channel attacks, 2009 3rd International Conference on Signals, Circuits and Systems (SCS), 2009. ,
DOI : 10.1109/ICSCS.2009.5412597
URL : https://hal.archives-ouvertes.fr/hal-00425523
Implementation and Evaluation of an SCA-Resistant Embedded Processor, Smart Card Research and Advanced Applications, pp.151-165, 2011. ,
DOI : 10.1007/978-3-642-27257-8_10
Stratgies pour scuriser les processeurs embarqus contre les attaques par canaux auxiliaires, 2012. ,
FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers, 2010 International Conference on Field Programmable Logic and Applications, pp.77-82, 2010. ,
DOI : 10.1109/FPL.2010.25
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.354.77
SCA-resistant embedded processors, Proceedings of the 26th Annual Computer Security Applications Conference on, ACSAC '10, pp.211-220, 2010. ,
DOI : 10.1145/1920261.1920293
Power Analysis Resistant AES Implementation with Instruction Set Extensions, Proceedings of the 2007 Cryptographic Hardware and Embedded Systems Workshop, pp.303-319, 2007. ,
DOI : 10.1007/978-3-540-74735-2_21
Power Analysis Attacks - Revealing the Secrets of Smart Cards, 2007. ,
A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks, Proceedings of the 23rd symposium on Integrated circuits and system design, SBCCI '10, 2010. ,
DOI : 10.1145/1854153.1854183
Prototype IC with WDDL and Differential Routing ??? DPA Resistance Assessment, Proceedings of the 2005 Cryptographic Hardware and Embedded Systems Workshop, pp.354-365, 2005. ,
DOI : 10.1007/11545262_26
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA, 2009 Design, Automation & Test in Europe Conference & Exhibition, pp.634-639, 2009. ,
DOI : 10.1109/DATE.2009.5090744
Non-deterministic Processors, Australasian Conference on Information Security and Privacy, 2001. ,
DOI : 10.1007/3-540-47719-5_11
Parallel Operation in the CDC 6600, AFIPS Proc. FJCC, pp.33-40, 1964. ,
An Efficient Algorithm for Exploiting Multiple Arithmetic Units, IBM Journal of Research and Development, vol.11, issue.1, pp.25-33, 1967. ,
DOI : 10.1147/rd.111.0025
Random Register Renaming to Foil DPA, Proceedings of the 2001 Cryptographic Hardware and Embedded Systems Workshop, pp.28-38, 2001. ,
DOI : 10.1007/3-540-44709-1_4
Instruction stream mutation for non-deterministic processors, Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors, pp.286-295, 2002. ,
DOI : 10.1109/ASAP.2002.1030727
RIJID, Proceedings of the 44th annual conference on Design automation, DAC '07, pp.489-492, 2007. ,
DOI : 10.1145/1278480.1278606
A unified framework for the analysis of side-channel key recovery attacks Advances in Cryptology-Eurocrypt, pp.443-461, 2009. ,